Change in coreboot[master]: sb/common/smihandler: Fix 16-bit read/write to PCI_COMMAND register
HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40742 )
Change subject: sb/common/smihandler: Fix 16-bit read/write to PCI_COMMAND register ......................................................................
sb/common/smihandler: Fix 16-bit read/write to PCI_COMMAND register
Change-Id: Ib403f5a231f86bdc60b956e72a4ae631aa6a3899 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/southbridge/intel/common/smihandler.c 1 file changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/40742/1
diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 7d4066d..7b27ce0 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -61,7 +61,7 @@
for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { - u32 reg32; + u16 reg16; pci_devfn_t dev = PCI_DEV(bus, slot, func);
val = pci_read_config32(dev, PCI_VENDOR_ID); @@ -71,9 +71,9 @@ continue;
/* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~PCI_COMMAND_MASTER; + pci_write_config16(dev, PCI_COMMAND, reg16);
/* If this is a bridge, then follow it. */ hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40742 )
Change subject: sb/common/smihandler: Fix 16-bit read/write to PCI_COMMAND register ......................................................................
Patch Set 1: Code-Review+1
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40742 )
Change subject: sb/common/smihandler: Fix 16-bit read/write to PCI_COMMAND register ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40742 )
Change subject: sb/common/smihandler: Fix 16-bit read/write to PCI_COMMAND register ......................................................................
sb/common/smihandler: Fix 16-bit read/write to PCI_COMMAND register
Change-Id: Ib403f5a231f86bdc60b956e72a4ae631aa6a3899 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/40742 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Reviewed-by: Nico Huber nico.h@gmx.de --- M src/southbridge/intel/common/smihandler.c 1 file changed, 4 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve
diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 7d4066d..7b27ce0 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -61,7 +61,7 @@
for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { - u32 reg32; + u16 reg16; pci_devfn_t dev = PCI_DEV(bus, slot, func);
val = pci_read_config32(dev, PCI_VENDOR_ID); @@ -71,9 +71,9 @@ continue;
/* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~PCI_COMMAND_MASTER; + pci_write_config16(dev, PCI_COMMAND, reg16);
/* If this is a bridge, then follow it. */ hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
-
HAOUAS Elyes (Code Review) -
Nico Huber (Code Review)
-
Patrick Georgi (Code Review)
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Paul Menzel (Code Review)