Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46134 )
Change subject: sb/intel/lnyxpoint: Set PCIe L1 substate capabilities register ......................................................................
sb/intel/lnyxpoint: Set PCIe L1 substate capabilities register
Copied from soc/intel/broadwell.
Test: build/boot gogole/beltino variants
Change-Id: Ib2ae3d9539de9f7e22975f00450d9d60d1fd938a Signed-off-by: Matt DeVillier matt.devillier@gmail.com --- M src/southbridge/intel/lynxpoint/pcie.c 1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/46134/1
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 42e002b..66e46d3 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -678,6 +678,12 @@ pci_update_config32(dev, 0x100, ~(1 << 29) & ~0xfffff, (1 << 29));
+ /* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */ + if (CONFIG(PCIEXP_L1_SUB_STATE)) + pci_update_config32(dev, 0x200, ~0xfffff, 0x001e); + else + pci_update_config32(dev, 0x200, ~0xfffff, 0); + if (is_lp) pci_or_config32(dev, 0x100, 1 << 29);
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46134 )
Change subject: sb/intel/lnyxpoint: Set PCIe L1 substate capabilities register ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
I'll test on B85M Pro4
https://review.coreboot.org/c/coreboot/+/46134/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46134/1//COMMIT_MSG@11 PS1, Line 11: gogole google doesn't have a googol boards yet 😜
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46134 )
Change subject: sb/intel/lnyxpoint: Set PCIe L1 substate capabilities register ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46134/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46134/1//COMMIT_MSG@7 PS1, Line 7: lnyxpoint Linux Point! 😄
Hello build bot (Jenkins), Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46134
to look at the new patch set (#2).
Change subject: sb/intel/lynxpoint: Set PCIe L1 substate capabilities register ......................................................................
sb/intel/lynxpoint: Set PCIe L1 substate capabilities register
Copied from soc/intel/broadwell.
Test: build/boot google/beltino variants
Change-Id: Ib2ae3d9539de9f7e22975f00450d9d60d1fd938a Signed-off-by: Matt DeVillier matt.devillier@gmail.com --- M src/southbridge/intel/lynxpoint/pcie.c 1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/46134/2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46134 )
Change subject: sb/intel/lynxpoint: Set PCIe L1 substate capabilities register ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/46134/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46134/2//COMMIT_MSG@11 PS2, Line 11: Test: build/boot google/beltino variants … and checked with lspci?
https://review.coreboot.org/c/coreboot/+/46134/2/src/southbridge/intel/lynxp... File src/southbridge/intel/lynxpoint/pcie.c:
https://review.coreboot.org/c/coreboot/+/46134/2/src/southbridge/intel/lynxp... PS2, Line 681: /* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */ Would be better to put the comment into the first branch? (But it’d be inconsistent with Broadwell then.)
Hello build bot (Jenkins), Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46134
to look at the new patch set (#3).
Change subject: sb/intel/lynxpoint: Set PCIe L1 substates capabilities register ......................................................................
sb/intel/lynxpoint: Set PCIe L1 substates capabilities register
Copied from soc/intel/broadwell.
Test: build/boot google/beltino variants, verify L1 PM substates listed under PCIe device capabilities
Change-Id: Ib2ae3d9539de9f7e22975f00450d9d60d1fd938a Signed-off-by: Matt DeVillier matt.devillier@gmail.com --- M src/southbridge/intel/lynxpoint/pcie.c 1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/46134/3
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46134 )
Change subject: sb/intel/lynxpoint: Set PCIe L1 substates capabilities register ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/46134/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46134/2//COMMIT_MSG@11 PS2, Line 11: Test: build/boot google/beltino variants
… and checked with lspci?
Done
https://review.coreboot.org/c/coreboot/+/46134/2/src/southbridge/intel/lynxp... File src/southbridge/intel/lynxpoint/pcie.c:
https://review.coreboot.org/c/coreboot/+/46134/2/src/southbridge/intel/lynxp... PS2, Line 681: /* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */
Would be better to put the comment into the first branch? (But it’d be inconsistent with Broadwell t […]
my preference would be to keep as-is for consistency, unless the comment was incorrect or unclear, and I don't believe that's the case here
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46134 )
Change subject: sb/intel/lynxpoint: Set PCIe L1 substates capabilities register ......................................................................
Patch Set 3: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/46134/2/src/southbridge/intel/lynxp... File src/southbridge/intel/lynxpoint/pcie.c:
https://review.coreboot.org/c/coreboot/+/46134/2/src/southbridge/intel/lynxp... PS2, Line 681: /* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */
my preference would be to keep as-is for consistency, unless the comment was incorrect or unclear, a […]
I'd rather keep it where it is
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46134 )
Change subject: sb/intel/lynxpoint: Set PCIe L1 substates capabilities register ......................................................................
Patch Set 3:
(3 comments)
https://review.coreboot.org/c/coreboot/+/46134/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46134/1//COMMIT_MSG@7 PS1, Line 7: lnyxpoint
Linux Point! 😄
Done
https://review.coreboot.org/c/coreboot/+/46134/1//COMMIT_MSG@11 PS1, Line 11: gogole
google doesn't have a googol boards yet 😜
Done
https://review.coreboot.org/c/coreboot/+/46134/2/src/southbridge/intel/lynxp... File src/southbridge/intel/lynxpoint/pcie.c:
https://review.coreboot.org/c/coreboot/+/46134/2/src/southbridge/intel/lynxp... PS2, Line 681: /* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */
I'd rather keep it where it is
Ack
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46134 )
Change subject: sb/intel/lynxpoint: Set PCIe L1 substates capabilities register ......................................................................
sb/intel/lynxpoint: Set PCIe L1 substates capabilities register
Copied from soc/intel/broadwell.
Test: build/boot google/beltino variants, verify L1 PM substates listed under PCIe device capabilities
Change-Id: Ib2ae3d9539de9f7e22975f00450d9d60d1fd938a Signed-off-by: Matt DeVillier matt.devillier@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46134 Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/southbridge/intel/lynxpoint/pcie.c 1 file changed, 6 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 077dcd6..2da14ed 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -676,6 +676,12 @@ else pci_update_config32(dev, 0x100, ~0xfffff, (1 << 29));
+ /* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */ + if (CONFIG(PCIEXP_L1_SUB_STATE)) + pci_update_config32(dev, 0x200, ~0xfffff, 0x001e); + else + pci_update_config32(dev, 0x200, ~0xfffff, 0); + if (is_lp) pci_or_config32(dev, 0x100, 1 << 29);