Matt DeVillier uploaded patch set #3 to this change.
sb/intel/lynxpoint: Set PCIe L1 substates capabilities register
Copied from soc/intel/broadwell.
Test: build/boot google/beltino variants, verify L1 PM substates
listed under PCIe device capabilities
Change-Id: Ib2ae3d9539de9f7e22975f00450d9d60d1fd938a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
---
M src/southbridge/intel/lynxpoint/pcie.c
1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/46134/3
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