Matt DeVillier has uploaded this change for review.

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sb/intel/lnyxpoint: Set PCIe L1 substate capabilities register

Copied from soc/intel/broadwell.

Test: build/boot gogole/beltino variants

Change-Id: Ib2ae3d9539de9f7e22975f00450d9d60d1fd938a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
---
M src/southbridge/intel/lynxpoint/pcie.c
1 file changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/46134/1

diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index 42e002b..66e46d3 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -678,6 +678,12 @@
 		pci_update_config32(dev, 0x100, ~(1 << 29) & ~0xfffff,
 			(1 << 29));
 
+	/* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */
+	if (CONFIG(PCIEXP_L1_SUB_STATE))
+		pci_update_config32(dev, 0x200, ~0xfffff, 0x001e);
+	else
+		pci_update_config32(dev, 0x200, ~0xfffff, 0);
+
 	if (is_lp)
 		pci_or_config32(dev, 0x100, 1 << 29);
 

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