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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81316?usp=email )
Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes
......................................................................
Patch Set 57:
(2 comments)
File src/soc/intel/xeon_sp/chip_gen6.c:
https://review.coreboot.org/c/coreboot/+/81316/comment/5a1b7ebc_24b08013 :
PS56, Line 56: res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
Good suggestion! Updated.
Well, this is the domain level where we describe the windows available for
allocation. It's probably just coincidence that it matches in position and
size what we usually tag fixed.
There are two things:
1. Xeon-SP hardware always forwards (or is configured by FSP to always forward) this, iow. makes it available for anything below DMI I guess (not fixed. maybe subtractive maybe not, doesn't matter to the resource allocator).
2. Developers are lazy and instead of adding all the "Fixed I/O Ranges Decoded by PCH" (table usually found it PCH datasheets) individually, we add a bulk 0..fff fixed resource, traditionally to the LPC/eSPI device as representative for all the legacy things in a PCH.
Now, 2. is already done in common/block/lpc code.
File src/soc/intel/xeon_sp/gnr/Kconfig:
https://review.coreboot.org/c/coreboot/+/81316/comment/79f4105d_cb487072 :
PS56, Line 17: select FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND
GNR still needs this ... the related discussion history is at: […]
That's why we do open-source, right? Because things that take a month or
two in open-source take years in proprietary projects.
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