Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32065
Change subject: nb/intel/sandybridge: Drop pch.h from sandybridge.h ......................................................................
nb/intel/sandybridge: Drop pch.h from sandybridge.h
Include pch.h in the source files instead in sandybridge.h.
Change-Id: I9e5b678e979a8d136d8d00b49486d0a882f77d81 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/northbridge/intel/sandybridge/gma.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/sandybridge.h M src/southbridge/intel/bd82x6x/acpi/pch.asl 4 files changed, 3 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/32065/1
diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 0d28d67..cb6782e 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -25,6 +25,7 @@ #include <drivers/intel/gma/libgfxinit.h> #include <southbridge/intel/bd82x6x/nvs.h> #include <drivers/intel/gma/opregion.h> +#include <southbridge/intel/bd82x6x/pch.h> #include <cbmem.h>
#include "chip.h" diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 3f62d10..4bfc58d 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -29,6 +29,7 @@ #include <mrc_cache.h> #include <southbridge/intel/bd82x6x/me.h> #include <southbridge/intel/common/smbus.h> +#include <southbridge/intel/bd82x6x/pch.h> #include <cpu/x86/msr.h> #include <delay.h> #include <lib.h> diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index e315fa4..92cb888 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -52,8 +52,6 @@ #define IOMMU_BASE1 0xfed90000ULL #define IOMMU_BASE2 0xfed91000ULL
-#include <southbridge/intel/bd82x6x/pch.h> - /* Everything below this line is ignored in the DSDT */ #ifndef __ACPI__ #include <cpu/intel/model_206ax/model_206ax.h> diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl index 72e284d..2018219 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pch.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl @@ -15,6 +15,7 @@ */
/* Intel Cougar Point PCH support */ +#include <southbridge/intel/bd82x6x/pch.h>
Scope() {
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32065
to look at the new patch set (#2).
Change subject: nb/intel/sandybridge: Drop pch.h from sandybridge.h ......................................................................
nb/intel/sandybridge: Drop pch.h from sandybridge.h
Include pch.h in the source files instead in sandybridge.h.
Change-Id: I9e5b678e979a8d136d8d00b49486d0a882f77d81 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/mainboard/asrock/b75pro3-m/romstage.c M src/mainboard/compulab/intense_pc/romstage.c M src/mainboard/google/link/romstage.c M src/mainboard/intel/dcp847ske/romstage.c M src/northbridge/intel/sandybridge/gma.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/sandybridge.h M src/southbridge/intel/bd82x6x/acpi/pch.asl 8 files changed, 7 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/32065/2
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32065
to look at the new patch set (#3).
Change subject: nb/intel/sandybridge: Drop pch.h from sandybridge.h ......................................................................
nb/intel/sandybridge: Drop pch.h from sandybridge.h
Include pch.h in the source files instead in sandybridge.h.
Change-Id: I9e5b678e979a8d136d8d00b49486d0a882f77d81 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/mainboard/asrock/b75pro3-m/romstage.c M src/mainboard/compulab/intense_pc/romstage.c M src/mainboard/google/link/romstage.c M src/mainboard/intel/dcp847ske/early_southbridge.c M src/mainboard/intel/dcp847ske/romstage.c M src/northbridge/intel/sandybridge/gma.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/sandybridge.h M src/southbridge/intel/bd82x6x/acpi/pch.asl 9 files changed, 8 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/32065/3
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32065
to look at the new patch set (#4).
Change subject: nb/intel/sandybridge: Drop pch.h from sandybridge.h ......................................................................
nb/intel/sandybridge: Drop pch.h from sandybridge.h
Include pch.h in the source files instead in sandybridge.h.
Tested on Lenovo T520 (Intel Sandy Bridge). Still boots to OS, no errors visible in dmesg.
Change-Id: I9e5b678e979a8d136d8d00b49486d0a882f77d81 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/mainboard/asrock/b75pro3-m/romstage.c M src/mainboard/compulab/intense_pc/romstage.c M src/mainboard/google/link/romstage.c M src/mainboard/intel/dcp847ske/early_southbridge.c M src/mainboard/intel/dcp847ske/romstage.c M src/northbridge/intel/sandybridge/gma.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/sandybridge.h M src/southbridge/intel/bd82x6x/acpi/pch.asl 9 files changed, 8 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/32065/4
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32065 )
Change subject: nb/intel/sandybridge: Drop pch.h from sandybridge.h ......................................................................
Patch Set 4: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32065 )
Change subject: nb/intel/sandybridge: Drop pch.h from sandybridge.h ......................................................................
nb/intel/sandybridge: Drop pch.h from sandybridge.h
Include pch.h in the source files instead in sandybridge.h.
Tested on Lenovo T520 (Intel Sandy Bridge). Still boots to OS, no errors visible in dmesg.
Change-Id: I9e5b678e979a8d136d8d00b49486d0a882f77d81 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/32065 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/asrock/b75pro3-m/romstage.c M src/mainboard/compulab/intense_pc/romstage.c M src/mainboard/google/link/romstage.c M src/mainboard/intel/dcp847ske/early_southbridge.c M src/mainboard/intel/dcp847ske/romstage.c M src/northbridge/intel/sandybridge/gma.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/sandybridge.h M src/southbridge/intel/bd82x6x/acpi/pch.asl 9 files changed, 8 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/mainboard/asrock/b75pro3-m/romstage.c b/src/mainboard/asrock/b75pro3-m/romstage.c index 5199124..cbd26a5 100644 --- a/src/mainboard/asrock/b75pro3-m/romstage.c +++ b/src/mainboard/asrock/b75pro3-m/romstage.c @@ -17,6 +17,7 @@ #include <device/pci_ops.h> #include <device/pnp_ops.h> #include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> #include <superio/nuvoton/nct6776/nct6776.h> #include <superio/nuvoton/common/nuvoton.h>
diff --git a/src/mainboard/compulab/intense_pc/romstage.c b/src/mainboard/compulab/intense_pc/romstage.c index dbd28c8..6d0b3af 100644 --- a/src/mainboard/compulab/intense_pc/romstage.c +++ b/src/mainboard/compulab/intense_pc/romstage.c @@ -18,6 +18,7 @@ #include <device/pci_ops.h> #include <northbridge/intel/sandybridge/raminit_native.h> #include <superio/smsc/sio1007/chip.h> +#include <southbridge/intel/bd82x6x/pch.h>
#define SIO_PORT 0x164e
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 66a503d0..8da1308 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -25,6 +25,7 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include "ec/google/chromeec/ec.h" #include <cbfs.h> diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c index 5100735..39aeb8f 100644 --- a/src/mainboard/intel/dcp847ske/early_southbridge.c +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -23,6 +23,7 @@ #include <device/pci_def.h> #include <console/console.h> #include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h>
#include "superio.h" #include "thermal.h" diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c index 24ec912..235ad22 100644 --- a/src/mainboard/intel/dcp847ske/romstage.c +++ b/src/mainboard/intel/dcp847ske/romstage.c @@ -23,6 +23,7 @@ #else #include <northbridge/intel/sandybridge/raminit.h> #endif +#include <southbridge/intel/bd82x6x/pch.h>
#if !CONFIG(USE_NATIVE_RAMINIT) void mainboard_fill_pei_data(struct pei_data *pei_data) diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 0d28d67..cb6782e 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -25,6 +25,7 @@ #include <drivers/intel/gma/libgfxinit.h> #include <southbridge/intel/bd82x6x/nvs.h> #include <drivers/intel/gma/opregion.h> +#include <southbridge/intel/bd82x6x/pch.h> #include <cbmem.h>
#include "chip.h" diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index c066634..050f4c2 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -29,6 +29,7 @@ #include <mrc_cache.h> #include <southbridge/intel/bd82x6x/me.h> #include <southbridge/intel/common/smbus.h> +#include <southbridge/intel/bd82x6x/pch.h> #include <cpu/x86/msr.h>
#include "raminit_native.h" diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index e315fa4..92cb888 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -52,8 +52,6 @@ #define IOMMU_BASE1 0xfed90000ULL #define IOMMU_BASE2 0xfed91000ULL
-#include <southbridge/intel/bd82x6x/pch.h> - /* Everything below this line is ignored in the DSDT */ #ifndef __ACPI__ #include <cpu/intel/model_206ax/model_206ax.h> diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl index 72e284d..2018219 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pch.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl @@ -15,6 +15,7 @@ */
/* Intel Cougar Point PCH support */ +#include <southbridge/intel/bd82x6x/pch.h>
Scope() {
-
Arthur Heymans (Code Review) -
Patrick Georgi (Code Review)
-
Patrick Rudolph (Code Review)