Patrick Rudolph has uploaded this change for review.

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nb/intel/sandybridge: Drop pch.h from sandybridge.h

Include pch.h in the source files instead in sandybridge.h.

Change-Id: I9e5b678e979a8d136d8d00b49486d0a882f77d81
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
---
M src/northbridge/intel/sandybridge/gma.c
M src/northbridge/intel/sandybridge/raminit.c
M src/northbridge/intel/sandybridge/sandybridge.h
M src/southbridge/intel/bd82x6x/acpi/pch.asl
4 files changed, 3 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/32065/1

diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c
index 0d28d67..cb6782e 100644
--- a/src/northbridge/intel/sandybridge/gma.c
+++ b/src/northbridge/intel/sandybridge/gma.c
@@ -25,6 +25,7 @@
 #include <drivers/intel/gma/libgfxinit.h>
 #include <southbridge/intel/bd82x6x/nvs.h>
 #include <drivers/intel/gma/opregion.h>
+#include <southbridge/intel/bd82x6x/pch.h>
 #include <cbmem.h>
 
 #include "chip.h"
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 3f62d10..4bfc58d 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -29,6 +29,7 @@
 #include <mrc_cache.h>
 #include <southbridge/intel/bd82x6x/me.h>
 #include <southbridge/intel/common/smbus.h>
+#include <southbridge/intel/bd82x6x/pch.h>
 #include <cpu/x86/msr.h>
 #include <delay.h>
 #include <lib.h>
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index e315fa4..92cb888 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -52,8 +52,6 @@
 #define IOMMU_BASE1		0xfed90000ULL
 #define IOMMU_BASE2		0xfed91000ULL
 
-#include <southbridge/intel/bd82x6x/pch.h>
-
 /* Everything below this line is ignored in the DSDT */
 #ifndef __ACPI__
 #include <cpu/intel/model_206ax/model_206ax.h>
diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl
index 72e284d..2018219 100644
--- a/src/southbridge/intel/bd82x6x/acpi/pch.asl
+++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl
@@ -15,6 +15,7 @@
  */
 
 /* Intel Cougar Point PCH support */
+#include <southbridge/intel/bd82x6x/pch.h>
 
 Scope(\)
 {

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