HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43283 )
Change subject: src: Remove redundant use of ACPI offset(0) ......................................................................
src: Remove redundant use of ACPI offset(0)
Change-Id: I260a79ef77025b4befbccc21f5999f89d90c1154 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/ec/compal/ene932/acpi/ec.asl M src/ec/google/chromeec/acpi/ec.asl M src/ec/google/chromeec/acpi/emem.asl M src/ec/quanta/it8518/acpi/ec.asl M src/ec/roda/it8518/acpi/ec.asl M src/mainboard/facebook/monolith/acpi/ec.asl M src/mainboard/lenovo/s230u/acpi/ec.asl M src/mainboard/lippert/frontrunner-af/dsdt.asl M src/mainboard/lippert/toucan-af/dsdt.asl M src/soc/amd/picasso/acpi/globalnvs.asl M src/soc/amd/stoneyridge/acpi/globalnvs.asl M src/soc/intel/apollolake/acpi/globalnvs.asl M src/soc/intel/baytrail/acpi/globalnvs.asl M src/soc/intel/broadwell/acpi/globalnvs.asl M src/soc/intel/broadwell/acpi/xhci.asl M src/soc/intel/cannonlake/acpi/scs.asl M src/soc/intel/denverton_ns/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/xhci.asl M src/southbridge/amd/cimx/sb800/acpi/fch.asl M src/southbridge/intel/bd82x6x/acpi/globalnvs.asl M src/southbridge/intel/bd82x6x/acpi/pch.asl M src/southbridge/intel/i82801ix/acpi/globalnvs.asl M src/southbridge/intel/i82801ix/acpi/ich9.asl M src/southbridge/intel/i82801jx/acpi/globalnvs.asl M src/southbridge/intel/i82801jx/acpi/ich10.asl M src/southbridge/intel/lynxpoint/acpi/globalnvs.asl M src/southbridge/intel/lynxpoint/acpi/usb.asl M src/superio/fintek/f81803a/acpi/superio.asl 29 files changed, 0 insertions(+), 29 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/43283/1
diff --git a/src/ec/compal/ene932/acpi/ec.asl b/src/ec/compal/ene932/acpi/ec.asl index 6b0997e..db53737 100644 --- a/src/ec/compal/ene932/acpi/ec.asl +++ b/src/ec/compal/ene932/acpi/ec.asl @@ -16,7 +16,6 @@ Field (ERAM, ByteAcc, Lock, Preserve) { // EC Name Space Configuration - Offset(0x00), , 1, // Reserved ; 00h.0 LCDS, 1, // 1= BACKLIGHT ON , 0= BACKLIGHT OFF ; 00h.1 , 6, // Reserved ; 00h.2 ~ 00h.6 diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index f8d4bdf..837bbd1 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -28,7 +28,6 @@ OperationRegion (ERAM, EmbeddedControl, 0x00, EC_ACPI_MEM_MAPPED_BEGIN) Field (ERAM, ByteAcc, Lock, Preserve) { - Offset (0x00), RAMV, 8, // EC RAM Version TSTB, 8, // Test Byte TSTC, 8, // Complement of Test Byte diff --git a/src/ec/google/chromeec/acpi/emem.asl b/src/ec/google/chromeec/acpi/emem.asl index 77a6f71..2a556ed 100644 --- a/src/ec/google/chromeec/acpi/emem.asl +++ b/src/ec/google/chromeec/acpi/emem.asl @@ -4,7 +4,6 @@ * EMEM data may be accessed through port 62/66 or through LPC at 900h. */
-Offset (0x00), TIN0, 8, // Temperature 0 TIN1, 8, // Temperature 1 TIN2, 8, // Temperature 2 diff --git a/src/ec/quanta/it8518/acpi/ec.asl b/src/ec/quanta/it8518/acpi/ec.asl index a3598be..5f2300a 100644 --- a/src/ec/quanta/it8518/acpi/ec.asl +++ b/src/ec/quanta/it8518/acpi/ec.asl @@ -16,7 +16,6 @@ OperationRegion(ERAM, EmbeddedControl, 0, 0xFF) Field (ERAM, ByteAcc, NoLock, Preserve) { - Offset(0x00), // [Configuration Space 0] , 1, // Reserved bit[0] ENGA, 1, // Enable Global attention ENHY, 1, // Enable Hotkey function diff --git a/src/ec/roda/it8518/acpi/ec.asl b/src/ec/roda/it8518/acpi/ec.asl index d500084..de121c6 100644 --- a/src/ec/roda/it8518/acpi/ec.asl +++ b/src/ec/roda/it8518/acpi/ec.asl @@ -14,7 +14,6 @@ OperationRegion(ERAM, EmbeddedControl, 0, 0xFF) Field (ERAM, ByteAcc, NoLock, Preserve) { - Offset(0x00), // [Configuration Space 0x0] Offset(0x02), // [Configuration Space 0x2] B0ST, 16, // Battery 0 State B0FC, 16, // Battery 0 Last Full Charge Capacity diff --git a/src/mainboard/facebook/monolith/acpi/ec.asl b/src/mainboard/facebook/monolith/acpi/ec.asl index 8aff541..5e72456 100644 --- a/src/mainboard/facebook/monolith/acpi/ec.asl +++ b/src/mainboard/facebook/monolith/acpi/ec.asl @@ -29,7 +29,6 @@ OperationRegion (ERAM, EmbeddedControl, 0x00, 0xFF) Field (ERAM, ByteAcc, NoLock, Preserve) { - Offset (0x00), CPUT, 8, }
diff --git a/src/mainboard/lenovo/s230u/acpi/ec.asl b/src/mainboard/lenovo/s230u/acpi/ec.asl index 888feac..20a9096 100644 --- a/src/mainboard/lenovo/s230u/acpi/ec.asl +++ b/src/mainboard/lenovo/s230u/acpi/ec.asl @@ -12,7 +12,6 @@ OperationRegion (ERAM, SystemMemory, (CONFIG_EC_BASE_ADDRESS + 0x100), 0x100) Field (ERAM, ByteAcc, Lock, Preserve) { - Offset(0x00), , 1, , 1, HKFA, 1, // FN lock (Hotkey / FN row toggle) diff --git a/src/mainboard/lippert/frontrunner-af/dsdt.asl b/src/mainboard/lippert/frontrunner-af/dsdt.asl index a6a7ea5..52a7cbc 100644 --- a/src/mainboard/lippert/frontrunner-af/dsdt.asl +++ b/src/mainboard/lippert/frontrunner-af/dsdt.asl @@ -135,7 +135,6 @@ PIOD, 0x00000008, } IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { - Offset(0x00), /* MiscControl */ , 1, T1EE, 1, T2EE, 1, diff --git a/src/mainboard/lippert/toucan-af/dsdt.asl b/src/mainboard/lippert/toucan-af/dsdt.asl index a6562f5..eb40daf 100644 --- a/src/mainboard/lippert/toucan-af/dsdt.asl +++ b/src/mainboard/lippert/toucan-af/dsdt.asl @@ -135,7 +135,6 @@ PIOD, 0x00000008, } IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { - Offset(0x00), /* MiscControl */ , 1, T1EE, 1, T2EE, 1, diff --git a/src/soc/amd/picasso/acpi/globalnvs.asl b/src/soc/amd/picasso/acpi/globalnvs.asl index 3ab35df..4a541e6 100644 --- a/src/soc/amd/picasso/acpi/globalnvs.asl +++ b/src/soc/amd/picasso/acpi/globalnvs.asl @@ -12,7 +12,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), PCNT, 8, // 0x00 - Processor Count PPCM, 8, // 0x01 - Max PPC State LIDS, 8, // 0x02 - LID State diff --git a/src/soc/amd/stoneyridge/acpi/globalnvs.asl b/src/soc/amd/stoneyridge/acpi/globalnvs.asl index 2865352..9189df0 100644 --- a/src/soc/amd/stoneyridge/acpi/globalnvs.asl +++ b/src/soc/amd/stoneyridge/acpi/globalnvs.asl @@ -12,7 +12,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), PCNT, 8, // 0x00 - Processor Count PPCM, 8, // 0x01 - Max PPC State LIDS, 8, // 0x02 - LID State diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl index 82f41b3..8b03713 100644 --- a/src/soc/intel/apollolake/acpi/globalnvs.asl +++ b/src/soc/intel/apollolake/acpi/globalnvs.asl @@ -12,7 +12,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), PCNT, 8, // 0x00 - Processor Count PPCM, 8, // 0x01 - Max PPC State LIDS, 8, // 0x02 - LID State diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl index 6cb68ba..7084ff2 100644 --- a/src/soc/intel/baytrail/acpi/globalnvs.asl +++ b/src/soc/intel/baytrail/acpi/globalnvs.asl @@ -16,7 +16,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), OSYS, 16, // 0x00 - Operating System SMIF, 8, // 0x02 - SMI function PRM0, 8, // 0x03 - SMI function parameter diff --git a/src/soc/intel/broadwell/acpi/globalnvs.asl b/src/soc/intel/broadwell/acpi/globalnvs.asl index 3c6c5f5..9a4a0b5 100644 --- a/src/soc/intel/broadwell/acpi/globalnvs.asl +++ b/src/soc/intel/broadwell/acpi/globalnvs.asl @@ -16,7 +16,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), OSYS, 16, // 0x00 - Operating System SMIF, 8, // 0x02 - SMI function PRM0, 8, // 0x03 - SMI function parameter diff --git a/src/soc/intel/broadwell/acpi/xhci.asl b/src/soc/intel/broadwell/acpi/xhci.asl index 22e3cbc..3d87751 100644 --- a/src/soc/intel/broadwell/acpi/xhci.asl +++ b/src/soc/intel/broadwell/acpi/xhci.asl @@ -12,7 +12,6 @@ OperationRegion (XPRT, PCI_Config, 0x00, 0x100) Field (XPRT, AnyAcc, NoLock, Preserve) { - Offset (0x0), DVID, 16, Offset (0x10), , 16, diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl index 8e1de1e..8e2ea3e 100644 --- a/src/soc/intel/cannonlake/acpi/scs.asl +++ b/src/soc/intel/cannonlake/acpi/scs.asl @@ -23,7 +23,6 @@
OperationRegion(SCSR, PCI_Config, 0x00, 0x100) Field(SCSR, WordAcc, NoLock, Preserve) { - Offset (0x0), /* PCI VID DID */ VDID, 32, Offset (0x84), /* PMECTRLSTATUS */ PMCR, 16, diff --git a/src/soc/intel/denverton_ns/acpi/globalnvs.asl b/src/soc/intel/denverton_ns/acpi/globalnvs.asl index f858cdf..36bb724 100644 --- a/src/soc/intel/denverton_ns/acpi/globalnvs.asl +++ b/src/soc/intel/denverton_ns/acpi/globalnvs.asl @@ -16,7 +16,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), OSYS, 16, // 0x00 - Operating System SMIF, 8, // 0x02 - SMI function PRM0, 8, // 0x03 - SMI function parameter diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index abcde94..bc99698 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -17,7 +17,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), OSYS, 16, // 0x00 - Operating System SMIF, 8, // 0x02 - SMI function PRM0, 8, // 0x03 - SMI function parameter diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl index 2f5d8b2..978c7e3 100644 --- a/src/soc/intel/skylake/acpi/xhci.asl +++ b/src/soc/intel/skylake/acpi/xhci.asl @@ -83,7 +83,6 @@ OperationRegion (XPRT, PCI_Config, 0x00, 0x100) Field (XPRT, AnyAcc, NoLock, Preserve) { - Offset (0x0), DVID, 16, /* VENDORID */ Offset (0x10), , 16, diff --git a/src/southbridge/amd/cimx/sb800/acpi/fch.asl b/src/southbridge/amd/cimx/sb800/acpi/fch.asl index 0c0150d..6091593 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/fch.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/fch.asl @@ -213,7 +213,6 @@ PIOD, 0x00000008, } IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { - Offset(0x00), /* MiscControl */ , 1, T1EE, 1, T2EE, 1, diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl index f994472..46096cc 100644 --- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl +++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl @@ -15,7 +15,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), OSYS, 16, // 0x00 - Operating System SMIF, 8, // 0x02 - SMI function PRM0, 8, // 0x03 - SMI function parameter diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl index 4f08a64..b3d12ff 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pch.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl @@ -63,7 +63,6 @@ OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x6c) Field(GPIO, ByteAcc, NoLock, Preserve) { - Offset(0x00), // GPIO Use Select GU00, 8, GU01, 8, GU02, 8, diff --git a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl index 3b6115f..d428f4a 100644 --- a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl @@ -16,7 +16,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), OSYS, 16, // 0x00 - Operating System SMIF, 8, // 0x02 - SMI function PRM0, 8, // 0x03 - SMI function parameter diff --git a/src/southbridge/intel/i82801ix/acpi/ich9.asl b/src/southbridge/intel/i82801ix/acpi/ich9.asl index 115c254..dcb3dd2 100644 --- a/src/southbridge/intel/i82801ix/acpi/ich9.asl +++ b/src/southbridge/intel/i82801ix/acpi/ich9.asl @@ -32,7 +32,6 @@ OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x3c) Field(GPIO, ByteAcc, NoLock, Preserve) { - Offset(0x00), // GPIO Use Select GU00, 8, GU01, 8, GU02, 8, diff --git a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl index 3b6115f..d428f4a 100644 --- a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl @@ -16,7 +16,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), OSYS, 16, // 0x00 - Operating System SMIF, 8, // 0x02 - SMI function PRM0, 8, // 0x03 - SMI function parameter diff --git a/src/southbridge/intel/i82801jx/acpi/ich10.asl b/src/southbridge/intel/i82801jx/acpi/ich10.asl index a79b8a3..66ea0e2 100644 --- a/src/southbridge/intel/i82801jx/acpi/ich10.asl +++ b/src/southbridge/intel/i82801jx/acpi/ich10.asl @@ -33,7 +33,6 @@ OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x3c) Field(GPIO, ByteAcc, NoLock, Preserve) { - Offset(0x00), // GPIO Use Select GU00, 8, GU01, 8, GU02, 8, diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl index 16c4b75..104574f 100644 --- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl +++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl @@ -15,7 +15,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), OSYS, 16, // 0x00 - Operating System SMIF, 8, // 0x02 - SMI function PRM0, 8, // 0x03 - SMI function parameter diff --git a/src/southbridge/intel/lynxpoint/acpi/usb.asl b/src/southbridge/intel/lynxpoint/acpi/usb.asl index 4fd4a8e..bf38c24 100644 --- a/src/southbridge/intel/lynxpoint/acpi/usb.asl +++ b/src/southbridge/intel/lynxpoint/acpi/usb.asl @@ -56,7 +56,6 @@ OperationRegion (XPRT, PCI_Config, 0x00, 0x100) Field (XPRT, AnyAcc, NoLock, Preserve) { - Offset (0x0), DVID, 16, Offset (0x10), , 16, diff --git a/src/superio/fintek/f81803a/acpi/superio.asl b/src/superio/fintek/f81803a/acpi/superio.asl index 302f2f4..e20f009 100644 --- a/src/superio/fintek/f81803a/acpi/superio.asl +++ b/src/superio/fintek/f81803a/acpi/superio.asl @@ -234,7 +234,6 @@ OperationRegion(APCx, SystemIO, APC5, 0x01) Field(APCx, ByteAcc, Nolock, Preserve) /* bits in PME ACPI CONTROL Reg 5*/ { - Offset(0x00), /*Control Reg 5 */ , 7, PSIN, 1 /* PSIN_FLAG */ }
Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43283 )
Change subject: src: Remove redundant use of ACPI offset(0) ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43283/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43283/1//COMMIT_MSG@8 PS1, Line 8: Might add short description with reason of this change.
Hello build bot (Jenkins), David Guckian, Frans Hendriks, Vanessa Eusebio, Alexander Couzens, Andrey Petrov, Patrick Rudolph, Wim Vervoorn, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43283
to look at the new patch set (#2).
Change subject: src: Remove redundant use of ACPI offset(0) ......................................................................
src: Remove redundant use of ACPI offset(0)
IASL version 20180927 and greater, detects Unnecessary/redundant uses of the Offset() operator within a Field Unit list. It then sends a remark "^ Unnecessary/redundant use of Offset"
example: OperationRegion (OPR1, SystemMemory, 0x100, 0x100) Field (OPR1) { Offset (0), // Never needed FLD1, 32, Offset (4), // Redundant, offset is already 4 (bytes) FLD2, 8, Offset (64), // OK use of Offset. FLD3, 16, }
We will have those remarks: dsdt.asl 14: Offset (0), Remark 2158 - ^ Unnecessary/redundant use of Offset operator
dsdt.asl 16: Offset (4), Remark 2158 - ^ Unnecessary/redundant use of Offset operator
Change-Id: I260a79ef77025b4befbccc21f5999f89d90c1154 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/ec/compal/ene932/acpi/ec.asl M src/ec/google/chromeec/acpi/ec.asl M src/ec/google/chromeec/acpi/emem.asl M src/ec/quanta/it8518/acpi/ec.asl M src/ec/roda/it8518/acpi/ec.asl M src/mainboard/facebook/monolith/acpi/ec.asl M src/mainboard/lenovo/s230u/acpi/ec.asl M src/mainboard/lippert/frontrunner-af/dsdt.asl M src/mainboard/lippert/toucan-af/dsdt.asl M src/soc/amd/picasso/acpi/globalnvs.asl M src/soc/amd/stoneyridge/acpi/globalnvs.asl M src/soc/intel/apollolake/acpi/globalnvs.asl M src/soc/intel/baytrail/acpi/globalnvs.asl M src/soc/intel/broadwell/acpi/globalnvs.asl M src/soc/intel/broadwell/acpi/xhci.asl M src/soc/intel/cannonlake/acpi/scs.asl M src/soc/intel/denverton_ns/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/xhci.asl M src/southbridge/amd/cimx/sb800/acpi/fch.asl M src/southbridge/intel/bd82x6x/acpi/globalnvs.asl M src/southbridge/intel/bd82x6x/acpi/pch.asl M src/southbridge/intel/i82801ix/acpi/globalnvs.asl M src/southbridge/intel/i82801ix/acpi/ich9.asl M src/southbridge/intel/i82801jx/acpi/globalnvs.asl M src/southbridge/intel/i82801jx/acpi/ich10.asl M src/southbridge/intel/lynxpoint/acpi/globalnvs.asl M src/southbridge/intel/lynxpoint/acpi/usb.asl M src/superio/fintek/f81803a/acpi/superio.asl 29 files changed, 0 insertions(+), 29 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/43283/2
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43283 )
Change subject: src: Remove redundant use of ACPI offset(0) ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43283/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43283/1//COMMIT_MSG@8 PS1, Line 8:
Might add short description with reason of this change.
done, thank you.
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43283 )
Change subject: src: Remove redundant use of ACPI offset(0) ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43283/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43283/1//COMMIT_MSG@8 PS1, Line 8:
done, thank you.
Done
Hello build bot (Jenkins), David Guckian, Frans Hendriks, Vanessa Eusebio, Alexander Couzens, Andrey Petrov, Patrick Rudolph, Wim Vervoorn, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43283
to look at the new patch set (#3).
Change subject: src: Remove redundant use of ACPI offset(0) ......................................................................
src: Remove redundant use of ACPI offset(0)
IASL version 20180927 and greater, detects Unnecessary/redundant uses of the Offset() operator within a Field Unit list. It then sends a remark "^ Unnecessary/redundant use of Offset"
example: OperationRegion (OPR1, SystemMemory, 0x100, 0x100) Field (OPR1) { Offset (0), // Never needed FLD1, 32, Offset (4), // Redundant, offset is already 4 (bytes) FLD2, 8, Offset (64), // OK use of Offset. FLD3, 16, }
We will have those remarks: dsdt.asl 14: Offset (0), Remark 2158 - ^ Unnecessary/redundant use of Offset operator
dsdt.asl 16: Offset (4), Remark 2158 - ^ Unnecessary/redundant use of Offset operator
Change-Id: I260a79ef77025b4befbccc21f5999f89d90c1154 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/ec/compal/ene932/acpi/ec.asl M src/ec/google/chromeec/acpi/ec.asl M src/ec/google/chromeec/acpi/emem.asl M src/ec/quanta/it8518/acpi/ec.asl M src/ec/roda/it8518/acpi/ec.asl M src/mainboard/facebook/monolith/acpi/ec.asl M src/mainboard/lenovo/s230u/acpi/ec.asl M src/mainboard/lippert/frontrunner-af/dsdt.asl M src/mainboard/lippert/toucan-af/dsdt.asl M src/soc/amd/picasso/acpi/globalnvs.asl M src/soc/amd/stoneyridge/acpi/globalnvs.asl M src/soc/intel/apollolake/acpi/globalnvs.asl M src/soc/intel/baytrail/acpi/globalnvs.asl M src/soc/intel/broadwell/acpi/globalnvs.asl M src/soc/intel/broadwell/acpi/xhci.asl M src/soc/intel/cannonlake/acpi/scs.asl M src/soc/intel/denverton_ns/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/xhci.asl M src/southbridge/amd/cimx/sb800/acpi/fch.asl M src/southbridge/intel/bd82x6x/acpi/globalnvs.asl M src/southbridge/intel/bd82x6x/acpi/pch.asl M src/southbridge/intel/i82801ix/acpi/globalnvs.asl M src/southbridge/intel/i82801ix/acpi/ich9.asl M src/southbridge/intel/i82801jx/acpi/globalnvs.asl M src/southbridge/intel/i82801jx/acpi/ich10.asl M src/southbridge/intel/lynxpoint/acpi/globalnvs.asl M src/southbridge/intel/lynxpoint/acpi/usb.asl M src/superio/fintek/f81803a/acpi/superio.asl 29 files changed, 0 insertions(+), 29 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/43283/3
Wim Vervoorn has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43283 )
Change subject: src: Remove redundant use of ACPI offset(0) ......................................................................
Patch Set 3:
(9 comments)
https://review.coreboot.org/c/coreboot/+/43283/3/src/ec/roda/it8518/acpi/ec.... File src/ec/roda/it8518/acpi/ec.asl:
https://review.coreboot.org/c/coreboot/+/43283/3/src/ec/roda/it8518/acpi/ec.... PS3, Line 17: Offset(0x00), // [Configuration Space 0x0] Here you lose the comment as well
https://review.coreboot.org/c/coreboot/+/43283/3/src/mainboard/lippert/front... File src/mainboard/lippert/frontrunner-af/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/43283/3/src/mainboard/lippert/front... PS3, Line 137: */ Here you lose the comment as well
https://review.coreboot.org/c/coreboot/+/43283/3/src/mainboard/lippert/touca... File src/mainboard/lippert/toucan-af/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/43283/3/src/mainboard/lippert/touca... PS3, Line 137: */ Here you lose the comment as well
https://review.coreboot.org/c/coreboot/+/43283/3/src/soc/intel/cannonlake/ac... File src/soc/intel/cannonlake/acpi/scs.asl:
https://review.coreboot.org/c/coreboot/+/43283/3/src/soc/intel/cannonlake/ac... PS3, Line 26: */ Here you lose the comment as well
https://review.coreboot.org/c/coreboot/+/43283/3/src/southbridge/amd/cimx/sb... File src/southbridge/amd/cimx/sb800/acpi/fch.asl:
https://review.coreboot.org/c/coreboot/+/43283/3/src/southbridge/amd/cimx/sb... PS3, Line 216: */ Here you lose the comment as well
https://review.coreboot.org/c/coreboot/+/43283/3/src/southbridge/intel/bd82x... File src/southbridge/intel/bd82x6x/acpi/pch.asl:
https://review.coreboot.org/c/coreboot/+/43283/3/src/southbridge/intel/bd82x... PS3, Line 66: Select Here you lose the comment as well
https://review.coreboot.org/c/coreboot/+/43283/3/src/southbridge/intel/i8280... File src/southbridge/intel/i82801ix/acpi/ich9.asl:
https://review.coreboot.org/c/coreboot/+/43283/3/src/southbridge/intel/i8280... PS3, Line 35: Select Here you lose the comment as well
https://review.coreboot.org/c/coreboot/+/43283/3/src/southbridge/intel/i8280... File src/southbridge/intel/i82801jx/acpi/ich10.asl:
https://review.coreboot.org/c/coreboot/+/43283/3/src/southbridge/intel/i8280... PS3, Line 36: Select Here you lose the comment as well
https://review.coreboot.org/c/coreboot/+/43283/3/src/superio/fintek/f81803a/... File src/superio/fintek/f81803a/acpi/superio.asl:
https://review.coreboot.org/c/coreboot/+/43283/3/src/superio/fintek/f81803a/... PS3, Line 237: */ Here you lose the comment as well
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43283 )
Change subject: src: Remove redundant use of ACPI offset(0) ......................................................................
Patch Set 3:
(9 comments)
Thank you
https://review.coreboot.org/c/coreboot/+/43283/3/src/ec/roda/it8518/acpi/ec.... File src/ec/roda/it8518/acpi/ec.asl:
https://review.coreboot.org/c/coreboot/+/43283/3/src/ec/roda/it8518/acpi/ec.... PS3, Line 17: Offset(0x00), // [Configuration Space 0x0]
Here you lose the comment as well
Done
https://review.coreboot.org/c/coreboot/+/43283/3/src/mainboard/lippert/front... File src/mainboard/lippert/frontrunner-af/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/43283/3/src/mainboard/lippert/front... PS3, Line 137: */
Here you lose the comment as well
Done
https://review.coreboot.org/c/coreboot/+/43283/3/src/mainboard/lippert/touca... File src/mainboard/lippert/toucan-af/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/43283/3/src/mainboard/lippert/touca... PS3, Line 137: */
Here you lose the comment as well
Done
https://review.coreboot.org/c/coreboot/+/43283/3/src/soc/intel/cannonlake/ac... File src/soc/intel/cannonlake/acpi/scs.asl:
https://review.coreboot.org/c/coreboot/+/43283/3/src/soc/intel/cannonlake/ac... PS3, Line 26: */
Here you lose the comment as well
Done
https://review.coreboot.org/c/coreboot/+/43283/3/src/southbridge/amd/cimx/sb... File src/southbridge/amd/cimx/sb800/acpi/fch.asl:
https://review.coreboot.org/c/coreboot/+/43283/3/src/southbridge/amd/cimx/sb... PS3, Line 216: */
Here you lose the comment as well
Done
https://review.coreboot.org/c/coreboot/+/43283/3/src/southbridge/intel/bd82x... File src/southbridge/intel/bd82x6x/acpi/pch.asl:
https://review.coreboot.org/c/coreboot/+/43283/3/src/southbridge/intel/bd82x... PS3, Line 66: Select
Here you lose the comment as well
Done
https://review.coreboot.org/c/coreboot/+/43283/3/src/southbridge/intel/i8280... File src/southbridge/intel/i82801ix/acpi/ich9.asl:
https://review.coreboot.org/c/coreboot/+/43283/3/src/southbridge/intel/i8280... PS3, Line 35: Select
Here you lose the comment as well
Done
https://review.coreboot.org/c/coreboot/+/43283/3/src/southbridge/intel/i8280... File src/southbridge/intel/i82801jx/acpi/ich10.asl:
https://review.coreboot.org/c/coreboot/+/43283/3/src/southbridge/intel/i8280... PS3, Line 36: Select
Here you lose the comment as well
Done
https://review.coreboot.org/c/coreboot/+/43283/3/src/superio/fintek/f81803a/... File src/superio/fintek/f81803a/acpi/superio.asl:
https://review.coreboot.org/c/coreboot/+/43283/3/src/superio/fintek/f81803a/... PS3, Line 237: */
Here you lose the comment as well
Done
Hello build bot (Jenkins), David Guckian, Frans Hendriks, Vanessa Eusebio, Alexander Couzens, Andrey Petrov, Patrick Rudolph, Wim Vervoorn, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43283
to look at the new patch set (#4).
Change subject: src: Remove redundant use of ACPI offset(0) ......................................................................
src: Remove redundant use of ACPI offset(0)
IASL version 20180927 and greater, detects Unnecessary/redundant uses of the Offset() operator within a Field Unit list. It then sends a remark "^ Unnecessary/redundant use of Offset"
example: OperationRegion (OPR1, SystemMemory, 0x100, 0x100) Field (OPR1) { Offset (0), // Never needed FLD1, 32, Offset (4), // Redundant, offset is already 4 (bytes) FLD2, 8, Offset (64), // OK use of Offset. FLD3, 16, }
We will have those remarks: dsdt.asl 14: Offset (0), Remark 2158 - ^ Unnecessary/redundant use of Offset operator
dsdt.asl 16: Offset (4), Remark 2158 - ^ Unnecessary/redundant use of Offset operator
Change-Id: I260a79ef77025b4befbccc21f5999f89d90c1154 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/ec/compal/ene932/acpi/ec.asl M src/ec/google/chromeec/acpi/ec.asl M src/ec/google/chromeec/acpi/emem.asl M src/ec/quanta/it8518/acpi/ec.asl M src/ec/roda/it8518/acpi/ec.asl M src/mainboard/facebook/monolith/acpi/ec.asl M src/mainboard/lenovo/s230u/acpi/ec.asl M src/mainboard/lippert/frontrunner-af/dsdt.asl M src/mainboard/lippert/toucan-af/dsdt.asl M src/soc/amd/picasso/acpi/globalnvs.asl M src/soc/amd/stoneyridge/acpi/globalnvs.asl M src/soc/intel/apollolake/acpi/globalnvs.asl M src/soc/intel/baytrail/acpi/globalnvs.asl M src/soc/intel/broadwell/acpi/globalnvs.asl M src/soc/intel/broadwell/acpi/xhci.asl M src/soc/intel/cannonlake/acpi/scs.asl M src/soc/intel/denverton_ns/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/xhci.asl M src/southbridge/amd/cimx/sb800/acpi/fch.asl M src/southbridge/intel/bd82x6x/acpi/globalnvs.asl M src/southbridge/intel/bd82x6x/acpi/pch.asl M src/southbridge/intel/i82801ix/acpi/globalnvs.asl M src/southbridge/intel/i82801ix/acpi/ich9.asl M src/southbridge/intel/i82801jx/acpi/globalnvs.asl M src/southbridge/intel/i82801jx/acpi/ich10.asl M src/southbridge/intel/lynxpoint/acpi/globalnvs.asl M src/southbridge/intel/lynxpoint/acpi/usb.asl M src/superio/fintek/f81803a/acpi/superio.asl 29 files changed, 10 insertions(+), 29 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/43283/4
Wim Vervoorn has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43283 )
Change subject: src: Remove redundant use of ACPI offset(0) ......................................................................
Patch Set 4:
(10 comments)
I overlooked some things last time. I have some new suggestions see the comments below
https://review.coreboot.org/c/coreboot/+/43283/4/src/ec/compal/ene932/acpi/e... File src/ec/compal/ene932/acpi/ec.asl:
https://review.coreboot.org/c/coreboot/+/43283/4/src/ec/compal/ene932/acpi/e... PS4, Line 19: , 1, // Reserved ; 00h.0 I think the leading comma is confusing (didn't notice before I am sorry)
https://review.coreboot.org/c/coreboot/+/43283/4/src/ec/quanta/it8518/acpi/e... File src/ec/quanta/it8518/acpi/ec.asl:
https://review.coreboot.org/c/coreboot/+/43283/4/src/ec/quanta/it8518/acpi/e... PS4, Line 20: , I think the leading comma is confusing (didn't notice before I am sorry)
https://review.coreboot.org/c/coreboot/+/43283/4/src/ec/roda/it8518/acpi/ec.... File src/ec/roda/it8518/acpi/ec.asl:
https://review.coreboot.org/c/coreboot/+/43283/4/src/ec/roda/it8518/acpi/ec.... PS4, Line 17: / I guess I was wrong here, now the comment doesn't really make sense any more
https://review.coreboot.org/c/coreboot/+/43283/4/src/mainboard/lenovo/s230u/... File src/mainboard/lenovo/s230u/acpi/ec.asl:
https://review.coreboot.org/c/coreboot/+/43283/4/src/mainboard/lenovo/s230u/... PS4, Line 15: , I think the leading comma is confusing (didn't notice before I am sorry)
https://review.coreboot.org/c/coreboot/+/43283/4/src/mainboard/lippert/front... File src/mainboard/lippert/frontrunner-af/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/43283/4/src/mainboard/lippert/front... PS4, Line 138: , I think the leading comma is confusing (didn't notice before I am sorry)
https://review.coreboot.org/c/coreboot/+/43283/4/src/mainboard/lippert/touca... File src/mainboard/lippert/toucan-af/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/43283/4/src/mainboard/lippert/touca... PS4, Line 138: , I think the leading comma is confusing (didn't notice before I am sorry)
https://review.coreboot.org/c/coreboot/+/43283/4/src/soc/intel/cannonlake/ac... File src/soc/intel/cannonlake/acpi/scs.asl:
https://review.coreboot.org/c/coreboot/+/43283/4/src/soc/intel/cannonlake/ac... PS4, Line 26: /* I guess the comment should be behind the entry here
https://review.coreboot.org/c/coreboot/+/43283/4/src/southbridge/amd/cimx/sb... File src/southbridge/amd/cimx/sb800/acpi/fch.asl:
https://review.coreboot.org/c/coreboot/+/43283/4/src/southbridge/amd/cimx/sb... PS4, Line 216: /* I think the leading comma is confusing (didn't notice before I am sorry)
https://review.coreboot.org/c/coreboot/+/43283/4/src/southbridge/intel/i8280... File src/southbridge/intel/i82801ix/acpi/ich9.asl:
https://review.coreboot.org/c/coreboot/+/43283/4/src/southbridge/intel/i8280... PS4, Line 35: / Comment behind the entry?
https://review.coreboot.org/c/coreboot/+/43283/4/src/superio/fintek/f81803a/... File src/superio/fintek/f81803a/acpi/superio.asl:
https://review.coreboot.org/c/coreboot/+/43283/4/src/superio/fintek/f81803a/... PS4, Line 237: /*Control Reg 5 */ I think the leading comma is confusing (didn't notice before I am sorry)
Hello build bot (Jenkins), David Guckian, Frans Hendriks, Vanessa Eusebio, Alexander Couzens, Andrey Petrov, Patrick Rudolph, Wim Vervoorn, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43283
to look at the new patch set (#5).
Change subject: src: Remove redundant use of ACPI offset(0) ......................................................................
src: Remove redundant use of ACPI offset(0)
IASL version 20180927 and greater, detects Unnecessary/redundant uses of the Offset() operator within a Field Unit list. It then sends a remark "^ Unnecessary/redundant use of Offset"
example: OperationRegion (OPR1, SystemMemory, 0x100, 0x100) Field (OPR1) { Offset (0), // Never needed FLD1, 32, Offset (4), // Redundant, offset is already 4 (bytes) FLD2, 8, Offset (64), // OK use of Offset. FLD3, 16, }
We will have those remarks: dsdt.asl 14: Offset (0), Remark 2158 - ^ Unnecessary/redundant use of Offset operator
dsdt.asl 16: Offset (4), Remark 2158 - ^ Unnecessary/redundant use of Offset operator
Change-Id: I260a79ef77025b4befbccc21f5999f89d90c1154 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/ec/compal/ene932/acpi/ec.asl M src/ec/google/chromeec/acpi/ec.asl M src/ec/google/chromeec/acpi/emem.asl M src/ec/quanta/it8518/acpi/ec.asl M src/ec/roda/it8518/acpi/ec.asl M src/mainboard/facebook/monolith/acpi/ec.asl M src/mainboard/lenovo/s230u/acpi/ec.asl M src/mainboard/lippert/frontrunner-af/dsdt.asl M src/mainboard/lippert/toucan-af/dsdt.asl M src/soc/amd/picasso/acpi/globalnvs.asl M src/soc/amd/stoneyridge/acpi/globalnvs.asl M src/soc/intel/apollolake/acpi/globalnvs.asl M src/soc/intel/baytrail/acpi/globalnvs.asl M src/soc/intel/broadwell/acpi/globalnvs.asl M src/soc/intel/broadwell/acpi/xhci.asl M src/soc/intel/cannonlake/acpi/scs.asl M src/soc/intel/denverton_ns/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/xhci.asl M src/southbridge/amd/cimx/sb800/acpi/fch.asl M src/southbridge/intel/bd82x6x/acpi/globalnvs.asl M src/southbridge/intel/bd82x6x/acpi/pch.asl M src/southbridge/intel/i82801ix/acpi/globalnvs.asl M src/southbridge/intel/i82801ix/acpi/ich9.asl M src/southbridge/intel/i82801jx/acpi/globalnvs.asl M src/southbridge/intel/i82801jx/acpi/ich10.asl M src/southbridge/intel/lynxpoint/acpi/globalnvs.asl M src/southbridge/intel/lynxpoint/acpi/usb.asl M src/superio/fintek/f81803a/acpi/superio.asl 29 files changed, 11 insertions(+), 37 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/43283/5
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43283 )
Change subject: src: Remove redundant use of ACPI offset(0) ......................................................................
Patch Set 4:
(3 comments)
Thx
https://review.coreboot.org/c/coreboot/+/43283/4/src/ec/compal/ene932/acpi/e... File src/ec/compal/ene932/acpi/ec.asl:
https://review.coreboot.org/c/coreboot/+/43283/4/src/ec/compal/ene932/acpi/e... PS4, Line 19: , 1, // Reserved ; 00h.0
I think the leading comma is confusing (didn't notice before I am sorry)
that comma is needed.
https://review.coreboot.org/c/coreboot/+/43283/4/src/ec/roda/it8518/acpi/ec.... File src/ec/roda/it8518/acpi/ec.asl:
https://review.coreboot.org/c/coreboot/+/43283/4/src/ec/roda/it8518/acpi/ec.... PS4, Line 17: /
I guess I was wrong here, now the comment doesn't really make sense any more
Done
https://review.coreboot.org/c/coreboot/+/43283/4/src/soc/intel/cannonlake/ac... File src/soc/intel/cannonlake/acpi/scs.asl:
https://review.coreboot.org/c/coreboot/+/43283/4/src/soc/intel/cannonlake/ac... PS4, Line 26: /*
I guess the comment should be behind the entry here
Done
Wim Vervoorn has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43283 )
Change subject: src: Remove redundant use of ACPI offset(0) ......................................................................
Patch Set 5: Code-Review+1
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43283 )
Change subject: src: Remove redundant use of ACPI offset(0) ......................................................................
Patch Set 5:
(8 comments)
https://review.coreboot.org/c/coreboot/+/43283/4/src/ec/compal/ene932/acpi/e... File src/ec/compal/ene932/acpi/ec.asl:
https://review.coreboot.org/c/coreboot/+/43283/4/src/ec/compal/ene932/acpi/e... PS4, Line 19: , 1, // Reserved ; 00h.0
that comma is needed.
Done
https://review.coreboot.org/c/coreboot/+/43283/4/src/ec/quanta/it8518/acpi/e... File src/ec/quanta/it8518/acpi/ec.asl:
https://review.coreboot.org/c/coreboot/+/43283/4/src/ec/quanta/it8518/acpi/e... PS4, Line 20: ,
I think the leading comma is confusing (didn't notice before I am sorry)
Done
https://review.coreboot.org/c/coreboot/+/43283/4/src/mainboard/lenovo/s230u/... File src/mainboard/lenovo/s230u/acpi/ec.asl:
https://review.coreboot.org/c/coreboot/+/43283/4/src/mainboard/lenovo/s230u/... PS4, Line 15: ,
I think the leading comma is confusing (didn't notice before I am sorry)
Done
https://review.coreboot.org/c/coreboot/+/43283/4/src/mainboard/lippert/front... File src/mainboard/lippert/frontrunner-af/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/43283/4/src/mainboard/lippert/front... PS4, Line 138: ,
I think the leading comma is confusing (didn't notice before I am sorry)
Done
https://review.coreboot.org/c/coreboot/+/43283/4/src/mainboard/lippert/touca... File src/mainboard/lippert/toucan-af/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/43283/4/src/mainboard/lippert/touca... PS4, Line 138: ,
I think the leading comma is confusing (didn't notice before I am sorry)
Done
https://review.coreboot.org/c/coreboot/+/43283/4/src/southbridge/amd/cimx/sb... File src/southbridge/amd/cimx/sb800/acpi/fch.asl:
https://review.coreboot.org/c/coreboot/+/43283/4/src/southbridge/amd/cimx/sb... PS4, Line 216: /*
I think the leading comma is confusing (didn't notice before I am sorry)
Done
https://review.coreboot.org/c/coreboot/+/43283/4/src/southbridge/intel/i8280... File src/southbridge/intel/i82801ix/acpi/ich9.asl:
https://review.coreboot.org/c/coreboot/+/43283/4/src/southbridge/intel/i8280... PS4, Line 35: /
Comment behind the entry?
Done
https://review.coreboot.org/c/coreboot/+/43283/4/src/superio/fintek/f81803a/... File src/superio/fintek/f81803a/acpi/superio.asl:
https://review.coreboot.org/c/coreboot/+/43283/4/src/superio/fintek/f81803a/... PS4, Line 237: /*Control Reg 5 */
I think the leading comma is confusing (didn't notice before I am sorry)
Done
Hello build bot (Jenkins), David Guckian, Frans Hendriks, Vanessa Eusebio, Alexander Couzens, Andrey Petrov, Patrick Rudolph, Wim Vervoorn, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43283
to look at the new patch set (#6).
Change subject: src: Remove redundant use of ACPI offset(0) ......................................................................
src: Remove redundant use of ACPI offset(0)
IASL version 20180927 and greater, detects Unnecessary/redundant uses of the Offset() operator within a Field Unit list. It then sends a remark "^ Unnecessary/redundant use of Offset"
example: OperationRegion (OPR1, SystemMemory, 0x100, 0x100) Field (OPR1) { Offset (0), // Never needed FLD1, 32, Offset (4), // Redundant, offset is already 4 (bytes) FLD2, 8, Offset (64), // OK use of Offset. FLD3, 16, }
We will have those remarks: dsdt.asl 14: Offset (0), Remark 2158 - ^ Unnecessary/redundant use of Offset operator
dsdt.asl 16: Offset (4), Remark 2158 - ^ Unnecessary/redundant use of Offset operator
Change-Id: I260a79ef77025b4befbccc21f5999f89d90c1154 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/ec/compal/ene932/acpi/ec.asl M src/ec/google/chromeec/acpi/ec.asl M src/ec/google/chromeec/acpi/emem.asl M src/ec/quanta/it8518/acpi/ec.asl M src/ec/roda/it8518/acpi/ec.asl M src/mainboard/facebook/monolith/acpi/ec.asl M src/mainboard/lenovo/s230u/acpi/ec.asl M src/mainboard/lippert/frontrunner-af/dsdt.asl M src/soc/amd/picasso/acpi/globalnvs.asl M src/soc/amd/stoneyridge/acpi/globalnvs.asl M src/soc/intel/apollolake/acpi/globalnvs.asl M src/soc/intel/baytrail/acpi/globalnvs.asl M src/soc/intel/broadwell/acpi/globalnvs.asl M src/soc/intel/broadwell/acpi/xhci.asl M src/soc/intel/cannonlake/acpi/scs.asl M src/soc/intel/denverton_ns/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/xhci.asl M src/southbridge/amd/cimx/sb800/acpi/fch.asl M src/southbridge/intel/bd82x6x/acpi/globalnvs.asl M src/southbridge/intel/bd82x6x/acpi/pch.asl M src/southbridge/intel/i82801ix/acpi/globalnvs.asl M src/southbridge/intel/i82801ix/acpi/ich9.asl M src/southbridge/intel/i82801jx/acpi/globalnvs.asl M src/southbridge/intel/i82801jx/acpi/ich10.asl M src/southbridge/intel/lynxpoint/acpi/globalnvs.asl M src/southbridge/intel/lynxpoint/acpi/usb.asl M src/superio/fintek/f81803a/acpi/superio.asl 28 files changed, 10 insertions(+), 35 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/43283/6
Hello build bot (Jenkins), David Guckian, Frans Hendriks, Vanessa Eusebio, Alexander Couzens, Andrey Petrov, Patrick Rudolph, Wim Vervoorn, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43283
to look at the new patch set (#8).
Change subject: src: Remove redundant use of ACPI offset(0) ......................................................................
src: Remove redundant use of ACPI offset(0)
IASL version 20180927 and greater, detects Unnecessary/redundant uses of the Offset() operator within a Field Unit list. It then sends a remark "^ Unnecessary/redundant use of Offset"
example: OperationRegion (OPR1, SystemMemory, 0x100, 0x100) Field (OPR1) { Offset (0), // Never needed FLD1, 32, Offset (4), // Redundant, offset is already 4 (bytes) FLD2, 8, Offset (64), // OK use of Offset. FLD3, 16, }
We will have those remarks: dsdt.asl 14: Offset (0), Remark 2158 - ^ Unnecessary/redundant use of Offset operator
dsdt.asl 16: Offset (4), Remark 2158 - ^ Unnecessary/redundant use of Offset operator
Change-Id: I260a79ef77025b4befbccc21f5999f89d90c1154 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/ec/compal/ene932/acpi/ec.asl M src/ec/google/chromeec/acpi/ec.asl M src/ec/google/chromeec/acpi/emem.asl M src/ec/quanta/it8518/acpi/ec.asl M src/ec/roda/it8518/acpi/ec.asl M src/mainboard/facebook/monolith/acpi/ec.asl M src/mainboard/lenovo/s230u/acpi/ec.asl M src/mainboard/lippert/frontrunner-af/dsdt.asl M src/soc/amd/picasso/acpi/globalnvs.asl M src/soc/amd/stoneyridge/acpi/globalnvs.asl M src/soc/intel/apollolake/acpi/globalnvs.asl M src/soc/intel/baytrail/acpi/globalnvs.asl M src/soc/intel/broadwell/acpi/globalnvs.asl M src/soc/intel/broadwell/acpi/xhci.asl M src/soc/intel/cannonlake/acpi/scs.asl M src/soc/intel/denverton_ns/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/xhci.asl M src/southbridge/amd/cimx/sb800/acpi/fch.asl M src/southbridge/intel/bd82x6x/acpi/globalnvs.asl M src/southbridge/intel/bd82x6x/acpi/pch.asl M src/southbridge/intel/i82801ix/acpi/globalnvs.asl M src/southbridge/intel/i82801ix/acpi/ich9.asl M src/southbridge/intel/i82801jx/acpi/globalnvs.asl M src/southbridge/intel/i82801jx/acpi/ich10.asl M src/southbridge/intel/lynxpoint/acpi/globalnvs.asl M src/southbridge/intel/lynxpoint/acpi/usb.asl M src/superio/fintek/f81803a/acpi/superio.asl M src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl M src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPciLib.esl 30 files changed, 10 insertions(+), 39 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/43283/8
Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43283 )
Change subject: src: Remove redundant use of ACPI offset(0) ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43283/9/src/southbridge/intel/bd82x... File src/southbridge/intel/bd82x6x/acpi/pch.asl:
https://review.coreboot.org/c/coreboot/+/43283/9/src/southbridge/intel/bd82x... PS9, Line 66: // GPIO Use Select nit: Add this comment at next line, after the GU00, 8.
Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43283 )
Change subject: src: Remove redundant use of ACPI offset(0) ......................................................................
Patch Set 9: Code-Review+2
Hello build bot (Jenkins), David Guckian, Frans Hendriks, Vanessa Eusebio, Alexander Couzens, Andrey Petrov, Patrick Rudolph, Wim Vervoorn, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43283
to look at the new patch set (#10).
Change subject: src: Remove redundant use of ACPI offset(0) ......................................................................
src: Remove redundant use of ACPI offset(0)
IASL version 20180927 and greater, detects Unnecessary/redundant uses of the Offset() operator within a Field Unit list. It then sends a remark "^ Unnecessary/redundant use of Offset"
example: OperationRegion (OPR1, SystemMemory, 0x100, 0x100) Field (OPR1) { Offset (0), // Never needed FLD1, 32, Offset (4), // Redundant, offset is already 4 (bytes) FLD2, 8, Offset (64), // OK use of Offset. FLD3, 16, }
We will have those remarks: dsdt.asl 14: Offset (0), Remark 2158 - ^ Unnecessary/redundant use of Offset operator
dsdt.asl 16: Offset (4), Remark 2158 - ^ Unnecessary/redundant use of Offset operator
Change-Id: I260a79ef77025b4befbccc21f5999f89d90c1154 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/ec/compal/ene932/acpi/ec.asl M src/ec/google/chromeec/acpi/ec.asl M src/ec/google/chromeec/acpi/emem.asl M src/ec/quanta/it8518/acpi/ec.asl M src/ec/roda/it8518/acpi/ec.asl M src/mainboard/facebook/monolith/acpi/ec.asl M src/mainboard/lenovo/s230u/acpi/ec.asl M src/mainboard/lippert/frontrunner-af/dsdt.asl M src/soc/amd/picasso/acpi/globalnvs.asl M src/soc/amd/stoneyridge/acpi/globalnvs.asl M src/soc/intel/apollolake/acpi/globalnvs.asl M src/soc/intel/baytrail/acpi/globalnvs.asl M src/soc/intel/broadwell/acpi/globalnvs.asl M src/soc/intel/broadwell/acpi/xhci.asl M src/soc/intel/cannonlake/acpi/scs.asl M src/soc/intel/denverton_ns/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/xhci.asl M src/southbridge/amd/cimx/sb800/acpi/fch.asl M src/southbridge/intel/bd82x6x/acpi/globalnvs.asl M src/southbridge/intel/bd82x6x/acpi/pch.asl M src/southbridge/intel/i82801ix/acpi/globalnvs.asl M src/southbridge/intel/i82801ix/acpi/ich9.asl M src/southbridge/intel/i82801jx/acpi/globalnvs.asl M src/southbridge/intel/i82801jx/acpi/ich10.asl M src/southbridge/intel/lynxpoint/acpi/globalnvs.asl M src/southbridge/intel/lynxpoint/acpi/usb.asl M src/superio/fintek/f81803a/acpi/superio.asl M src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl M src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPciLib.esl 30 files changed, 10 insertions(+), 40 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/43283/10
Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43283 )
Change subject: src: Remove redundant use of ACPI offset(0) ......................................................................
Patch Set 10: Code-Review+2
Wim Vervoorn has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43283 )
Change subject: src: Remove redundant use of ACPI offset(0) ......................................................................
Patch Set 10: Code-Review+1
Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43283 )
Change subject: src: Remove redundant use of ACPI offset(0) ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43283/9/src/southbridge/intel/bd82x... File src/southbridge/intel/bd82x6x/acpi/pch.asl:
https://review.coreboot.org/c/coreboot/+/43283/9/src/southbridge/intel/bd82x... PS9, Line 66: // GPIO Use Select
nit: Add this comment at next line, after the GU00, 8.
Done
Felix Held has uploaded a new patch set (#11) to the change originally created by HAOUAS Elyes. ( https://review.coreboot.org/c/coreboot/+/43283 )
Change subject: src: Remove redundant use of ACPI offset(0) ......................................................................
src: Remove redundant use of ACPI offset(0)
IASL version 20180927 and greater, detects Unnecessary/redundant uses of the Offset() operator within a Field Unit list. It then sends a remark "^ Unnecessary/redundant use of Offset"
example: OperationRegion (OPR1, SystemMemory, 0x100, 0x100) Field (OPR1) { Offset (0), // Never needed FLD1, 32, Offset (4), // Redundant, offset is already 4 (bytes) FLD2, 8, Offset (64), // OK use of Offset. FLD3, 16, }
We will have those remarks: dsdt.asl 14: Offset (0), Remark 2158 - ^ Unnecessary/redundant use of Offset operator
dsdt.asl 16: Offset (4), Remark 2158 - ^ Unnecessary/redundant use of Offset operator
Change-Id: I260a79ef77025b4befbccc21f5999f89d90c1154 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/ec/compal/ene932/acpi/ec.asl M src/ec/google/chromeec/acpi/ec.asl M src/ec/google/chromeec/acpi/emem.asl M src/ec/quanta/it8518/acpi/ec.asl M src/ec/roda/it8518/acpi/ec.asl M src/mainboard/facebook/monolith/acpi/ec.asl M src/mainboard/lenovo/s230u/acpi/ec.asl M src/mainboard/lippert/frontrunner-af/dsdt.asl M src/soc/amd/picasso/acpi/globalnvs.asl M src/soc/amd/stoneyridge/acpi/globalnvs.asl M src/soc/intel/apollolake/acpi/globalnvs.asl M src/soc/intel/baytrail/acpi/globalnvs.asl M src/soc/intel/broadwell/pch/acpi/globalnvs.asl M src/soc/intel/broadwell/pch/acpi/xhci.asl M src/soc/intel/cannonlake/acpi/scs.asl M src/soc/intel/denverton_ns/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/xhci.asl M src/southbridge/amd/cimx/sb800/acpi/fch.asl M src/southbridge/intel/bd82x6x/acpi/globalnvs.asl M src/southbridge/intel/bd82x6x/acpi/pch.asl M src/southbridge/intel/i82801ix/acpi/globalnvs.asl M src/southbridge/intel/i82801ix/acpi/ich9.asl M src/southbridge/intel/i82801jx/acpi/globalnvs.asl M src/southbridge/intel/i82801jx/acpi/ich10.asl M src/southbridge/intel/lynxpoint/acpi/globalnvs.asl M src/southbridge/intel/lynxpoint/acpi/xhci.asl M src/superio/fintek/f81803a/acpi/superio.asl M src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl M src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPciLib.esl 30 files changed, 10 insertions(+), 40 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/43283/11
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43283 )
Change subject: src: Remove redundant use of ACPI offset(0) ......................................................................
Patch Set 11: Code-Review+1
did a manual rebase, so this can land upstream. since i did the rebase, i should probably only give it a +1 and not a +2
Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43283 )
Change subject: src: Remove redundant use of ACPI offset(0) ......................................................................
Patch Set 11: Code-Review+2
Jason Glenesk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43283 )
Change subject: src: Remove redundant use of ACPI offset(0) ......................................................................
Patch Set 11: Code-Review+1
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43283 )
Change subject: src: Remove redundant use of ACPI offset(0) ......................................................................
src: Remove redundant use of ACPI offset(0)
IASL version 20180927 and greater, detects Unnecessary/redundant uses of the Offset() operator within a Field Unit list. It then sends a remark "^ Unnecessary/redundant use of Offset"
example: OperationRegion (OPR1, SystemMemory, 0x100, 0x100) Field (OPR1) { Offset (0), // Never needed FLD1, 32, Offset (4), // Redundant, offset is already 4 (bytes) FLD2, 8, Offset (64), // OK use of Offset. FLD3, 16, }
We will have those remarks: dsdt.asl 14: Offset (0), Remark 2158 - ^ Unnecessary/redundant use of Offset operator
dsdt.asl 16: Offset (4), Remark 2158 - ^ Unnecessary/redundant use of Offset operator
Change-Id: I260a79ef77025b4befbccc21f5999f89d90c1154 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/43283 Reviewed-by: Felix Held felix-coreboot@felixheld.de Reviewed-by: Marshall Dawson marshalldawson3rd@gmail.com Reviewed-by: Jason Glenesk jason.glenesk@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/ec/compal/ene932/acpi/ec.asl M src/ec/google/chromeec/acpi/ec.asl M src/ec/google/chromeec/acpi/emem.asl M src/ec/quanta/it8518/acpi/ec.asl M src/ec/roda/it8518/acpi/ec.asl M src/mainboard/facebook/monolith/acpi/ec.asl M src/mainboard/lenovo/s230u/acpi/ec.asl M src/mainboard/lippert/frontrunner-af/dsdt.asl M src/soc/amd/picasso/acpi/globalnvs.asl M src/soc/amd/stoneyridge/acpi/globalnvs.asl M src/soc/intel/apollolake/acpi/globalnvs.asl M src/soc/intel/baytrail/acpi/globalnvs.asl M src/soc/intel/broadwell/pch/acpi/globalnvs.asl M src/soc/intel/broadwell/pch/acpi/xhci.asl M src/soc/intel/cannonlake/acpi/scs.asl M src/soc/intel/denverton_ns/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/xhci.asl M src/southbridge/amd/cimx/sb800/acpi/fch.asl M src/southbridge/intel/bd82x6x/acpi/globalnvs.asl M src/southbridge/intel/bd82x6x/acpi/pch.asl M src/southbridge/intel/i82801ix/acpi/globalnvs.asl M src/southbridge/intel/i82801ix/acpi/ich9.asl M src/southbridge/intel/i82801jx/acpi/globalnvs.asl M src/southbridge/intel/i82801jx/acpi/ich10.asl M src/southbridge/intel/lynxpoint/acpi/globalnvs.asl M src/southbridge/intel/lynxpoint/acpi/xhci.asl M src/superio/fintek/f81803a/acpi/superio.asl M src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl M src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPciLib.esl 30 files changed, 10 insertions(+), 40 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, but someone else must approve Marshall Dawson: Looks good to me, approved Jason Glenesk: Looks good to me, but someone else must approve
diff --git a/src/ec/compal/ene932/acpi/ec.asl b/src/ec/compal/ene932/acpi/ec.asl index 6b0997e..c4fa3a3 100644 --- a/src/ec/compal/ene932/acpi/ec.asl +++ b/src/ec/compal/ene932/acpi/ec.asl @@ -16,8 +16,7 @@ Field (ERAM, ByteAcc, Lock, Preserve) { // EC Name Space Configuration - Offset(0x00), - , 1, // Reserved ; 00h.0 + , 1, // Reserved ; 00h.0 LCDS, 1, // 1= BACKLIGHT ON , 0= BACKLIGHT OFF ; 00h.1 , 6, // Reserved ; 00h.2 ~ 00h.6 HTBN, 8, // HOTKEY_BUTTON_NUMBER ; 01h For ABO Hot Key Function diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index ce2455f..218d08b 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -31,7 +31,6 @@ OperationRegion (ERAM, EmbeddedControl, 0x00, EC_ACPI_MEM_MAPPED_BEGIN) Field (ERAM, ByteAcc, Lock, Preserve) { - Offset (0x00), RAMV, 8, // EC RAM Version TSTB, 8, // Test Byte TSTC, 8, // Complement of Test Byte diff --git a/src/ec/google/chromeec/acpi/emem.asl b/src/ec/google/chromeec/acpi/emem.asl index 77a6f71..2a556ed 100644 --- a/src/ec/google/chromeec/acpi/emem.asl +++ b/src/ec/google/chromeec/acpi/emem.asl @@ -4,7 +4,6 @@ * EMEM data may be accessed through port 62/66 or through LPC at 900h. */
-Offset (0x00), TIN0, 8, // Temperature 0 TIN1, 8, // Temperature 1 TIN2, 8, // Temperature 2 diff --git a/src/ec/quanta/it8518/acpi/ec.asl b/src/ec/quanta/it8518/acpi/ec.asl index a3598be..093593c 100644 --- a/src/ec/quanta/it8518/acpi/ec.asl +++ b/src/ec/quanta/it8518/acpi/ec.asl @@ -16,7 +16,7 @@ OperationRegion(ERAM, EmbeddedControl, 0, 0xFF) Field (ERAM, ByteAcc, NoLock, Preserve) { - Offset(0x00), // [Configuration Space 0] + // [Configuration Space 0] , 1, // Reserved bit[0] ENGA, 1, // Enable Global attention ENHY, 1, // Enable Hotkey function diff --git a/src/ec/roda/it8518/acpi/ec.asl b/src/ec/roda/it8518/acpi/ec.asl index d500084..de121c6 100644 --- a/src/ec/roda/it8518/acpi/ec.asl +++ b/src/ec/roda/it8518/acpi/ec.asl @@ -14,7 +14,6 @@ OperationRegion(ERAM, EmbeddedControl, 0, 0xFF) Field (ERAM, ByteAcc, NoLock, Preserve) { - Offset(0x00), // [Configuration Space 0x0] Offset(0x02), // [Configuration Space 0x2] B0ST, 16, // Battery 0 State B0FC, 16, // Battery 0 Last Full Charge Capacity diff --git a/src/mainboard/facebook/monolith/acpi/ec.asl b/src/mainboard/facebook/monolith/acpi/ec.asl index e729e01..d9a0729 100644 --- a/src/mainboard/facebook/monolith/acpi/ec.asl +++ b/src/mainboard/facebook/monolith/acpi/ec.asl @@ -29,7 +29,6 @@ OperationRegion (ERAM, EmbeddedControl, 0x00, 0xFF) Field (ERAM, ByteAcc, NoLock, Preserve) { - Offset (0x00), CPUT, 8, }
diff --git a/src/mainboard/lenovo/s230u/acpi/ec.asl b/src/mainboard/lenovo/s230u/acpi/ec.asl index 888feac..20a9096 100644 --- a/src/mainboard/lenovo/s230u/acpi/ec.asl +++ b/src/mainboard/lenovo/s230u/acpi/ec.asl @@ -12,7 +12,6 @@ OperationRegion (ERAM, SystemMemory, (CONFIG_EC_BASE_ADDRESS + 0x100), 0x100) Field (ERAM, ByteAcc, Lock, Preserve) { - Offset(0x00), , 1, , 1, HKFA, 1, // FN lock (Hotkey / FN row toggle) diff --git a/src/mainboard/lippert/frontrunner-af/dsdt.asl b/src/mainboard/lippert/frontrunner-af/dsdt.asl index ffae0d9..e0804ed 100644 --- a/src/mainboard/lippert/frontrunner-af/dsdt.asl +++ b/src/mainboard/lippert/frontrunner-af/dsdt.asl @@ -134,8 +134,7 @@ PIOD, 0x00000008, } IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { - Offset(0x00), /* MiscControl */ - , 1, + , 1, /* MiscControl */ T1EE, 1, T2EE, 1, Offset(0x01), /* MiscStatus */ diff --git a/src/soc/amd/picasso/acpi/globalnvs.asl b/src/soc/amd/picasso/acpi/globalnvs.asl index 6790a5f..70964921 100644 --- a/src/soc/amd/picasso/acpi/globalnvs.asl +++ b/src/soc/amd/picasso/acpi/globalnvs.asl @@ -15,7 +15,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), PCNT, 8, // 0x00 - Processor Count LIDS, 8, // 0x01 - LID State PWRS, 8, // 0x02 - AC Power State diff --git a/src/soc/amd/stoneyridge/acpi/globalnvs.asl b/src/soc/amd/stoneyridge/acpi/globalnvs.asl index 0acc408..8bfc7b2 100644 --- a/src/soc/amd/stoneyridge/acpi/globalnvs.asl +++ b/src/soc/amd/stoneyridge/acpi/globalnvs.asl @@ -12,7 +12,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), PCNT, 8, // 0x00 - Processor Count LIDS, 8, // 0x01 - LID State PWRS, 8, // 0x02 - AC Power State diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl index 82f41b3..8b03713 100644 --- a/src/soc/intel/apollolake/acpi/globalnvs.asl +++ b/src/soc/intel/apollolake/acpi/globalnvs.asl @@ -12,7 +12,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), PCNT, 8, // 0x00 - Processor Count PPCM, 8, // 0x01 - Max PPC State LIDS, 8, // 0x02 - LID State diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl index c472d06..ad77a83 100644 --- a/src/soc/intel/baytrail/acpi/globalnvs.asl +++ b/src/soc/intel/baytrail/acpi/globalnvs.asl @@ -17,7 +17,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), OSYS, 16, /* 0x00 - Operating System */ SMIF, 8, /* 0x02 - SMI function */ PRM0, 8, /* 0x03 - SMI function parameter */ diff --git a/src/soc/intel/broadwell/pch/acpi/globalnvs.asl b/src/soc/intel/broadwell/pch/acpi/globalnvs.asl index 06ca564..7ee7e13 100644 --- a/src/soc/intel/broadwell/pch/acpi/globalnvs.asl +++ b/src/soc/intel/broadwell/pch/acpi/globalnvs.asl @@ -16,7 +16,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), OSYS, 16, // 0x00 - Operating System SMIF, 8, // 0x02 - SMI function PRM0, 8, // 0x03 - SMI function parameter diff --git a/src/soc/intel/broadwell/pch/acpi/xhci.asl b/src/soc/intel/broadwell/pch/acpi/xhci.asl index 4bdd310..0656a6c 100644 --- a/src/soc/intel/broadwell/pch/acpi/xhci.asl +++ b/src/soc/intel/broadwell/pch/acpi/xhci.asl @@ -12,7 +12,6 @@ OperationRegion (XPRT, PCI_Config, 0, 0x100) Field (XPRT, AnyAcc, NoLock, Preserve) { - Offset (0x0), DVID, 16, Offset (0x10), , 16, diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl index 8e1de1e..462e65a 100644 --- a/src/soc/intel/cannonlake/acpi/scs.asl +++ b/src/soc/intel/cannonlake/acpi/scs.asl @@ -23,8 +23,7 @@
OperationRegion(SCSR, PCI_Config, 0x00, 0x100) Field(SCSR, WordAcc, NoLock, Preserve) { - Offset (0x0), /* PCI VID DID */ - VDID, 32, + VDID, 32, /* PCI VID DID */ Offset (0x84), /* PMECTRLSTATUS */ PMCR, 16, Offset (0xA2), /* PG_CONFIG */ diff --git a/src/soc/intel/denverton_ns/acpi/globalnvs.asl b/src/soc/intel/denverton_ns/acpi/globalnvs.asl index 7ce6c7a..4725cec 100644 --- a/src/soc/intel/denverton_ns/acpi/globalnvs.asl +++ b/src/soc/intel/denverton_ns/acpi/globalnvs.asl @@ -16,7 +16,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), OSYS, 16, // 0x00 - Operating System SMIF, 8, // 0x02 - SMI function PRM0, 8, // 0x03 - SMI function parameter diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index abcde94..bc99698 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -17,7 +17,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), OSYS, 16, // 0x00 - Operating System SMIF, 8, // 0x02 - SMI function PRM0, 8, // 0x03 - SMI function parameter diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl index 2f5d8b2..978c7e3 100644 --- a/src/soc/intel/skylake/acpi/xhci.asl +++ b/src/soc/intel/skylake/acpi/xhci.asl @@ -83,7 +83,6 @@ OperationRegion (XPRT, PCI_Config, 0x00, 0x100) Field (XPRT, AnyAcc, NoLock, Preserve) { - Offset (0x0), DVID, 16, /* VENDORID */ Offset (0x10), , 16, diff --git a/src/southbridge/amd/cimx/sb800/acpi/fch.asl b/src/southbridge/amd/cimx/sb800/acpi/fch.asl index 0c0150d..0986b69 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/fch.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/fch.asl @@ -213,8 +213,7 @@ PIOD, 0x00000008, } IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { - Offset(0x00), /* MiscControl */ - , 1, + , 1, /* MiscControl */ T1EE, 1, T2EE, 1, Offset(0x01), /* MiscStatus */ diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl index f994472..46096cc 100644 --- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl +++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl @@ -15,7 +15,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), OSYS, 16, // 0x00 - Operating System SMIF, 8, // 0x02 - SMI function PRM0, 8, // 0x03 - SMI function parameter diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl index 4f08a64..4a033ab 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pch.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl @@ -63,8 +63,7 @@ OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x6c) Field(GPIO, ByteAcc, NoLock, Preserve) { - Offset(0x00), // GPIO Use Select - GU00, 8, + GU00, 8, // GPIO Use Select GU01, 8, GU02, 8, GU03, 8, diff --git a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl index 0a0f255..5c9e26e 100644 --- a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl @@ -15,7 +15,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), OSYS, 16, // 0x00 - Operating System SMIF, 8, // 0x02 - SMI function PRM0, 8, // 0x03 - SMI function parameter diff --git a/src/southbridge/intel/i82801ix/acpi/ich9.asl b/src/southbridge/intel/i82801ix/acpi/ich9.asl index 25a756e..f720505 100644 --- a/src/southbridge/intel/i82801ix/acpi/ich9.asl +++ b/src/southbridge/intel/i82801ix/acpi/ich9.asl @@ -32,8 +32,7 @@ OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x3c) Field(GPIO, ByteAcc, NoLock, Preserve) { - Offset(0x00), // GPIO Use Select - GU00, 8, + GU00, 8, // GPIO Use Select GU01, 8, GU02, 8, GU03, 8, diff --git a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl index 0a0f255..5c9e26e 100644 --- a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl @@ -15,7 +15,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), OSYS, 16, // 0x00 - Operating System SMIF, 8, // 0x02 - SMI function PRM0, 8, // 0x03 - SMI function parameter diff --git a/src/southbridge/intel/i82801jx/acpi/ich10.asl b/src/southbridge/intel/i82801jx/acpi/ich10.asl index e62f8a1..d6136af 100644 --- a/src/southbridge/intel/i82801jx/acpi/ich10.asl +++ b/src/southbridge/intel/i82801jx/acpi/ich10.asl @@ -33,7 +33,7 @@ OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x3c) Field(GPIO, ByteAcc, NoLock, Preserve) { - Offset(0x00), // GPIO Use Select + // GPIO Use Select GU00, 8, GU01, 8, GU02, 8, diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl index ccf9b08..482718a 100644 --- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl +++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl @@ -16,7 +16,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), OSYS, 16, // 0x00 - Operating System SMIF, 8, // 0x02 - SMI function PRM0, 8, // 0x03 - SMI function parameter diff --git a/src/southbridge/intel/lynxpoint/acpi/xhci.asl b/src/southbridge/intel/lynxpoint/acpi/xhci.asl index fbeb562..a65b1f6 100644 --- a/src/southbridge/intel/lynxpoint/acpi/xhci.asl +++ b/src/southbridge/intel/lynxpoint/acpi/xhci.asl @@ -12,7 +12,6 @@ OperationRegion (XPRT, PCI_Config, 0, 0x100) Field (XPRT, AnyAcc, NoLock, Preserve) { - Offset (0x0), DVID, 16, Offset (0x10), , 16, diff --git a/src/superio/fintek/f81803a/acpi/superio.asl b/src/superio/fintek/f81803a/acpi/superio.asl index 4e2c525..87574a8 100644 --- a/src/superio/fintek/f81803a/acpi/superio.asl +++ b/src/superio/fintek/f81803a/acpi/superio.asl @@ -234,9 +234,8 @@ OperationRegion(APCx, SystemIO, APC5, 0x01) Field(APCx, ByteAcc, Nolock, Preserve) /* bits in PME ACPI CONTROL Reg 5*/ { - Offset(0x00), /*Control Reg 5 */ - , 7, - PSIN, 1 /* PSIN_FLAG */ + , 7, /*Control Reg 5 */ + PSIN, 1 /* PSIN_FLAG */ }
/* routine to clear PSIN_FLAG in ACPI_CONTROL_REG_5 of SIO */ diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl index 463093c..5d545b1 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl @@ -142,7 +142,6 @@ Add (Arg1, Local0, Local0) OperationRegion(varOperationRegionMmio, SystemMemory, Local0, 0x4) Field(varOperationRegionMmio, DWordAcc, NoLock, Preserve) { - Offset (0x0), varPciReg32, 32, } return (varPciReg32) @@ -160,7 +159,6 @@ Add (Arg1, Local0, Local0) OperationRegion(varOperationRegionMmio, SystemMemory, Local0, 0x4) Field(varOperationRegionMmio, DWordAcc, NoLock, Preserve) { - Offset (0x0), varPciReg32, 32, } Store (Arg2, varPciReg32) diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPciLib.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPciLib.esl index 9dba662..342c646 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPciLib.esl +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPciLib.esl @@ -55,7 +55,6 @@ Add (Arg1, Local0, Local0) OperationRegion(varOperationRegionMmio, SystemMemory, Local0, 0x4) Field(varOperationRegionMmio, DWordAcc, NoLock, Preserve) { - Offset (0x0), varPciReg32, 32, } return (varPciReg32) @@ -73,7 +72,6 @@ Add (Arg1, Local0, Local0) OperationRegion(varOperationRegionMmio, SystemMemory, Local0, 0x4) Field(varOperationRegionMmio, DWordAcc, NoLock, Preserve) { - Offset (0x0), varPciReg32, 32, } Store (Arg2, varPciReg32)
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