Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40805 )
Change subject: mainboard/google/kahlee: support Realtek RTL8822CE WLAN ......................................................................
mainboard/google/kahlee: support Realtek RTL8822CE WLAN
gpio70 is assigned to use as WLAN rst in new schematic to fullful RTK RTL8822CE power sequence: WLAN rst will need to be active at least 50ms after WLAN power on.
Also in order to keep the rst low in consistency, change default gpio70 to low.
BUG=b:154357210 BRANCH=master TEST=emerge-grunt coreboot
Change-Id: I98c8afe42b7f92016f83483acbb3b9ae64b159f7 Signed-off-by: Kevin Chiu Kevin.Chiu@quantatw.com --- M src/mainboard/google/kahlee/variants/baseboard/gpio.c M src/mainboard/google/kahlee/variants/careena/variant.c 2 files changed, 8 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/40805/1
diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index 4fb60b1..e5c02d5 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -43,7 +43,7 @@ PAD_GPO(GPIO_40, LOW),
/* GPIO_70 - WLAN_PE_RST_L */ - PAD_GPO(GPIO_70, HIGH), + PAD_GPO(GPIO_70, LOW),
/* GPIO_74 - LPC_CLK0_EC_R */ PAD_NF(GPIO_74, LPCCLK0, PULL_DOWN), diff --git a/src/mainboard/google/kahlee/variants/careena/variant.c b/src/mainboard/google/kahlee/variants/careena/variant.c index d35ec48..fb71b9f 100644 --- a/src/mainboard/google/kahlee/variants/careena/variant.c +++ b/src/mainboard/google/kahlee/variants/careena/variant.c @@ -16,6 +16,8 @@ #include <ec/google/chromeec/ec.h> #include <baseboard/variants.h> #include <variant/sku.h> +#include <gpio.h> +#include <variant/gpio.h>
void variant_romstage_entry(int s3_resume) { @@ -35,4 +37,9 @@ break; } } + + /* Config WLAN RST - GPIO70 PU: release RST */ + /* From RTK RTL8822CE spec, WLAN RST needs to be active */ + /* at least 50 ms since WLAN power on */ + gpio_set(GPIO_70, 1); }
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40805 )
Change subject: mainboard/google/kahlee: support Realtek RTL8822CE WLAN ......................................................................
Patch Set 1: Code-Review-1
1) This would require an RO spin, which we're trying to avoid. 2) There's also an issue of the pcie reset which needs to be 6ms.
I think doing a hardware spin and an RO spin is a heavy-handed way to solve this, especially since I think we can solve it in RW by changing AGESA.
Can we leave this on hold for now?
Kevin Chiu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40805 )
Change subject: mainboard/google/kahlee: support Realtek RTL8822CE WLAN ......................................................................
Patch Set 1:
Patch Set 1: Code-Review-1
- This would require an RO spin, which we're trying to avoid.
- There's also an issue of the pcie reset which needs to be 6ms.
I think doing a hardware spin and an RO spin is a heavy-handed way to solve this, especially since I think we can solve it in RW by changing AGESA.
Can we leave this on hold for now?
Hi Martin, sure, as you said the cost is too much for only one wlan support. it's even better if rw could solve everything we need and I'd glad to abandon this one. thank you!
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40805 )
Change subject: mainboard/google/kahlee: support Realtek RTL8822CE WLAN ......................................................................
Patch Set 1: -Code-Review
(3 comments)
https://review.coreboot.org/c/coreboot/+/40805/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40805/1//COMMIT_MSG@7 PS1, Line 7: support Realtek RTL8822CE WLAN Hold WLAN PCIe reset low at boot
The change is to support the realtek chip, but that's not the effect of the change.
https://review.coreboot.org/c/coreboot/+/40805/1/src/mainboard/google/kahlee... File src/mainboard/google/kahlee/variants/careena/variant.c:
https://review.coreboot.org/c/coreboot/+/40805/1/src/mainboard/google/kahlee... PS1, Line 40: Maybe add a check for board id? I guess it shouldn't matter for this change since the previous RO already had it set to 1, so this would be a NOP for the previous boards. And it wasn't even connected, so NOP NOP.
https://review.coreboot.org/c/coreboot/+/40805/1/src/mainboard/google/kahlee... PS1, Line 41: /* Config WLAN RST - GPIO70 PU: release RST */ : /* From RTK RTL8822CE spec, WLAN RST needs to be active */ : /* at least 50 ms since WLAN power on */ Update to coreboot multiline comment style: /* * Config WLAN RST - GPIO70 PU: release RST * From RTK RTL8822CE spec, WLAN RST needs to be active * at least 50 ms since WLAN power on */
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40805 )
Change subject: mainboard/google/kahlee: support Realtek RTL8822CE WLAN ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40805/1/src/mainboard/google/kahlee... File src/mainboard/google/kahlee/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/40805/1/src/mainboard/google/kahlee... PS1, Line 46: , This change should probably go into a careena version of the file as well so that other boards don't get it. I'm not sure if everyone chose not to stuff this path.
Hello Kevin Chiu, build bot (Jenkins), Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40805
to look at the new patch set (#2).
Change subject: mainboard/google/kahlee: Hold WLAN PCIe reset low at boot ......................................................................
mainboard/google/kahlee: Hold WLAN PCIe reset low at boot
gpio70 is assigned to use as WLAN rst in new schematic to fullful RTK RTL8822CE power sequence: WLAN rst will need to be active at least 50ms after WLAN power on.
Also in order to keep the rst low in consistency, change default gpio70 to low.
BUG=b:154357210 BRANCH=master TEST=emerge-grunt coreboot
Change-Id: I98c8afe42b7f92016f83483acbb3b9ae64b159f7 Signed-off-by: Kevin Chiu Kevin.Chiu@quantatw.com --- M src/mainboard/google/kahlee/variants/baseboard/gpio.c M src/mainboard/google/kahlee/variants/careena/variant.c 2 files changed, 10 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/40805/2
Kevin Chiu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40805 )
Change subject: mainboard/google/kahlee: Hold WLAN PCIe reset low at boot ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40805/1/src/mainboard/google/kahlee... File src/mainboard/google/kahlee/variants/careena/variant.c:
https://review.coreboot.org/c/coreboot/+/40805/1/src/mainboard/google/kahlee... PS1, Line 40:
Maybe add a check for board id? I guess it shouldn't matter for this change since the previous RO a […]
Hi Martin, actually our EE would also propose one specific board id for this schematic change. I'll do more test on the rework M/B. thanks.
Kevin Chiu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40805 )
Change subject: mainboard/google/kahlee: Hold WLAN PCIe reset low at boot ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40805/1/src/mainboard/google/kahlee... File src/mainboard/google/kahlee/variants/careena/variant.c:
https://review.coreboot.org/c/coreboot/+/40805/1/src/mainboard/google/kahlee... PS1, Line 41: /* Config WLAN RST - GPIO70 PU: release RST */ : /* From RTK RTL8822CE spec, WLAN RST needs to be active */ : /* at least 50 ms since WLAN power on */
Update to coreboot multiline comment style: […]
Done
Hello Kevin Chiu, build bot (Jenkins), Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40805
to look at the new patch set (#3).
Change subject: mainboard/google/kahlee: Hold WLAN PCIe reset low at boot ......................................................................
mainboard/google/kahlee: Hold WLAN PCIe reset low at boot
gpio70 is assigned to use as WLAN rst in new schematic to fullful RTK RTL8822CE power sequence: WLAN rst will need to be active at least 50ms after WLAN power on.
Also in order to keep the rst low in consistency, change default gpio70 to low.
BUG=b:154357210 BRANCH=master TEST=emerge-grunt coreboot
Change-Id: I98c8afe42b7f92016f83483acbb3b9ae64b159f7 Signed-off-by: Kevin Chiu Kevin.Chiu@quantatw.com --- M src/mainboard/google/kahlee/variants/baseboard/gpio.c M src/mainboard/google/kahlee/variants/careena/include/variant/sku.h M src/mainboard/google/kahlee/variants/careena/variant.c 3 files changed, 28 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/40805/3
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40805 )
Change subject: mainboard/google/kahlee: Hold WLAN PCIe reset low at boot ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40805/3/src/mainboard/google/kahlee... File src/mainboard/google/kahlee/variants/careena/variant.c:
https://review.coreboot.org/c/coreboot/+/40805/3/src/mainboard/google/kahlee... PS3, Line 44: switch(bid) { space required before the open parenthesis '('
Kevin Chiu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40805 )
Change subject: mainboard/google/kahlee: Hold WLAN PCIe reset low at boot ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40805/1/src/mainboard/google/kahlee... File src/mainboard/google/kahlee/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/40805/1/src/mainboard/google/kahlee... PS1, Line 46: ,
This change should probably go into a careena version of the file as well so that other boards don't […]
Hi Martin, so we may need to overwrite variant_early_gpio_table in variant which means the whole "gpio_set_stage_reset" structure I got to copy for variant usage. is it ok? thanks.
Hello Kevin Chiu, build bot (Jenkins), Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40805
to look at the new patch set (#4).
Change subject: mainboard/google/kahlee: Hold WLAN PCIe reset low at boot ......................................................................
mainboard/google/kahlee: Hold WLAN PCIe reset low at boot
gpio70 is assigned to use as WLAN rst in new schematic to fullful RTK RTL8822CE power sequence: WLAN rst will need to be active at least 50ms after WLAN power on.
Also in order to keep the rst low in consistency, change default gpio70 to low.
BUG=b:154357210 BRANCH=master TEST=emerge-grunt coreboot
Change-Id: I98c8afe42b7f92016f83483acbb3b9ae64b159f7 Signed-off-by: Kevin Chiu Kevin.Chiu@quantatw.com --- M src/mainboard/google/kahlee/variants/baseboard/gpio.c M src/mainboard/google/kahlee/variants/careena/include/variant/sku.h M src/mainboard/google/kahlee/variants/careena/variant.c 3 files changed, 28 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/40805/4
Hello Kevin Chiu, build bot (Jenkins), Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40805
to look at the new patch set (#5).
Change subject: mainboard/google/kahlee: Hold WLAN PCIe reset low at boot ......................................................................
mainboard/google/kahlee: Hold WLAN PCIe reset low at boot
gpio70 is assigned to use as WLAN rst in new schematic to fullful RTK RTL8822CE power sequence: WLAN rst will need to be active at least 50ms after WLAN power on.
Also in order to keep the rst low in consistency, change default gpio70 to low.
BUG=b:154357210 BRANCH=master TEST=emerge-grunt coreboot
Change-Id: I98c8afe42b7f92016f83483acbb3b9ae64b159f7 Signed-off-by: Kevin Chiu Kevin.Chiu@quantatw.com --- M src/mainboard/google/kahlee/variants/baseboard/gpio.c M src/mainboard/google/kahlee/variants/careena/include/variant/sku.h M src/mainboard/google/kahlee/variants/careena/variant.c 3 files changed, 27 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/40805/5
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40805 )
Change subject: mainboard/google/kahlee: Hold WLAN PCIe reset low at boot ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40805/1/src/mainboard/google/kahlee... File src/mainboard/google/kahlee/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/40805/1/src/mainboard/google/kahlee... PS1, Line 46: ,
Hi Martin, […]
You could just remove GPIO 70 from this list and add a secondary (weak) gpio init in bootblock to initialize this GPIO high for the baseboard and everything still using it. Then you can initialize it as low for careena.
I guess I'm also ok at this point just overriding this whole table for careena, but I think my first suggestion would be cleaner.
Hello Kevin Chiu, build bot (Jenkins), Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40805
to look at the new patch set (#6).
Change subject: mainboard/google/kahlee: Hold WLAN PCIe reset low at boot for mordin ......................................................................
mainboard/google/kahlee: Hold WLAN PCIe reset low at boot for mordin
gpio70 is assigned to use as WLAN rst in new schematic to fullful RTK RTL8822CE power sequence: WLAN rst will need to be active at least 50ms after WLAN power on.
Also in order to keep the rst low in consistency, override default gpio70 to low.
BUG=b:154357210,b:154848243 BRANCH=master TEST=emerge-grunt coreboot
Change-Id: I98c8afe42b7f92016f83483acbb3b9ae64b159f7 Signed-off-by: Kevin Chiu Kevin.Chiu@quantatw.com --- M src/mainboard/google/kahlee/variants/careena/include/variant/sku.h M src/mainboard/google/kahlee/variants/careena/variant.c 2 files changed, 37 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/40805/6
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40805 )
Change subject: mainboard/google/kahlee: Hold WLAN PCIe reset low at boot for mordin ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40805/6/src/mainboard/google/kahlee... File src/mainboard/google/kahlee/variants/careena/variant.c:
https://review.coreboot.org/c/coreboot/+/40805/6/src/mainboard/google/kahlee... PS6, Line 24: PAD_GPO(GPIO_70, LOW), please, no spaces at the start of a line
Hello Kevin Chiu, build bot (Jenkins), Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40805
to look at the new patch set (#7).
Change subject: mainboard/google/kahlee: Hold WLAN PCIe reset low at boot for mordin ......................................................................
mainboard/google/kahlee: Hold WLAN PCIe reset low at boot for mordin
gpio70 is assigned to use as WLAN rst in new schematic to fullful RTK RTL8822CE power sequence: WLAN rst will need to be active at least 50ms after WLAN power on.
Also in order to keep the rst low in consistency, override default gpio70 to low.
BUG=b:154357210,b:154848243 BRANCH=master TEST=emerge-grunt coreboot
Change-Id: I98c8afe42b7f92016f83483acbb3b9ae64b159f7 Signed-off-by: Kevin Chiu Kevin.Chiu@quantatw.com --- M src/mainboard/google/kahlee/variants/careena/include/variant/sku.h M src/mainboard/google/kahlee/variants/careena/variant.c 2 files changed, 37 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/40805/7
Kevin Chiu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40805 )
Change subject: mainboard/google/kahlee: Hold WLAN PCIe reset low at boot for mordin ......................................................................
Patch Set 7:
(2 comments)
https://review.coreboot.org/c/coreboot/+/40805/1/src/mainboard/google/kahlee... File src/mainboard/google/kahlee/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/40805/1/src/mainboard/google/kahlee... PS1, Line 46: ,
You could just remove GPIO 70 from this list and add a secondary (weak) gpio init in bootblock to in […]
Done, thank you!
https://review.coreboot.org/c/coreboot/+/40805/6/src/mainboard/google/kahlee... File src/mainboard/google/kahlee/variants/careena/variant.c:
https://review.coreboot.org/c/coreboot/+/40805/6/src/mainboard/google/kahlee... PS6, Line 24: PAD_GPO(GPIO_70, LOW),
please, no spaces at the start of a line
Done
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40805 )
Change subject: mainboard/google/kahlee: Hold WLAN PCIe reset low at boot for mordin ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40805/7/src/mainboard/google/kahlee... File src/mainboard/google/kahlee/variants/careena/include/variant/sku.h:
https://review.coreboot.org/c/coreboot/+/40805/7/src/mainboard/google/kahlee... PS7, Line 28: BDV_UNKNOWN = -1, : BDV_CAREENA_BARLA_PROTO = 3, : BDV_CAREENA_BARLA_EVT = 4, : BDV_CAREENA_BARLA_DVT = 5, : BDV_CAREENA_BARLA_PVT = 6, : BDV_MORDIN_PVT We don't want to encode board phases in the code.
Hello Kevin Chiu, build bot (Jenkins), Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40805
to look at the new patch set (#8).
Change subject: mainboard/google/kahlee: Hold WLAN PCIe reset low at boot for mordin ......................................................................
mainboard/google/kahlee: Hold WLAN PCIe reset low at boot for mordin
gpio70 is assigned to use as WLAN rst in new schematic to fullful RTK RTL8822CE power sequence: WLAN rst will need to be active at least 50ms after WLAN power on.
Also in order to keep the rst low in consistency, override default gpio70 to low.
BUG=b:154357210,b:154848243 BRANCH=master TEST=emerge-grunt coreboot
Change-Id: I98c8afe42b7f92016f83483acbb3b9ae64b159f7 Signed-off-by: Kevin Chiu Kevin.Chiu@quantatw.com --- M src/mainboard/google/kahlee/variants/careena/variant.c 1 file changed, 24 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/40805/8
Kevin Chiu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40805 )
Change subject: mainboard/google/kahlee: Hold WLAN PCIe reset low at boot for mordin ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40805/7/src/mainboard/google/kahlee... File src/mainboard/google/kahlee/variants/careena/include/variant/sku.h:
https://review.coreboot.org/c/coreboot/+/40805/7/src/mainboard/google/kahlee... PS7, Line 28: BDV_UNKNOWN = -1, : BDV_CAREENA_BARLA_PROTO = 3, : BDV_CAREENA_BARLA_EVT = 4, : BDV_CAREENA_BARLA_DVT = 5, : BDV_CAREENA_BARLA_PVT = 6, : BDV_MORDIN_PVT
We don't want to encode board phases in the code.
Done, removed, thank you!
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40805 )
Change subject: mainboard/google/kahlee: Hold WLAN PCIe reset low at boot for mordin ......................................................................
Patch Set 9:
(2 comments)
https://review.coreboot.org/c/coreboot/+/40805/9//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40805/9//COMMIT_MSG@7 PS9, Line 7: mainboard mb
https://review.coreboot.org/c/coreboot/+/40805/9//COMMIT_MSG@9 PS9, Line 9: fullful fulfill
Hello Kevin Chiu, build bot (Jenkins), Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40805
to look at the new patch set (#10).
Change subject: mb/google/kahlee: Hold WLAN PCIe reset low at boot for mordin ......................................................................
mb/google/kahlee: Hold WLAN PCIe reset low at boot for mordin
gpio70 is assigned to use as WLAN rst in new schematic to fulfill RTK RTL8822CE power sequence: WLAN rst will need to be active at least 50ms after WLAN power on.
Also in order to keep the rst low in consistency, override default gpio70 to low.
BUG=b:154357210,b:154848243 BRANCH=master TEST=emerge-grunt coreboot
Change-Id: I98c8afe42b7f92016f83483acbb3b9ae64b159f7 Signed-off-by: Kevin Chiu Kevin.Chiu@quantatw.com --- M src/mainboard/google/kahlee/variants/careena/variant.c 1 file changed, 24 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/40805/10
Kevin Chiu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40805 )
Change subject: mb/google/kahlee: Hold WLAN PCIe reset low at boot for mordin ......................................................................
Patch Set 10:
(2 comments)
https://review.coreboot.org/c/coreboot/+/40805/9//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40805/9//COMMIT_MSG@7 PS9, Line 7: mainboard
mb
Done
https://review.coreboot.org/c/coreboot/+/40805/9//COMMIT_MSG@9 PS9, Line 9: fullful
fulfill
Done
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40805 )
Change subject: mb/google/kahlee: Hold WLAN PCIe reset low at boot for mordin ......................................................................
Patch Set 10: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40805 )
Change subject: mb/google/kahlee: Hold WLAN PCIe reset low at boot for mordin ......................................................................
Patch Set 10: Code-Review+1
Hello Kevin Chiu, build bot (Jenkins), Martin Roth, Paul Menzel,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40805
to look at the new patch set (#11).
Change subject: mb/google/kahlee: Hold WLAN PCIe reset low at boot for mordin ......................................................................
mb/google/kahlee: Hold WLAN PCIe reset low at boot for mordin
gpio70 is assigned to use as WLAN rst in new schematic to fulfill RTK RTL8822CE power sequence: WLAN rst will need to be active at least 50ms after WLAN power on.
Also in order to keep the rst low in consistency, override default gpio70 to low.
BUG=b:154357210,b:154848243 BRANCH=master TEST=emerge-grunt coreboot
Change-Id: I98c8afe42b7f92016f83483acbb3b9ae64b159f7 Signed-off-by: Kevin Chiu Kevin.Chiu@quantatw.com --- M src/mainboard/google/kahlee/variants/careena/Makefile.inc M src/mainboard/google/kahlee/variants/careena/variant.c 2 files changed, 25 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/40805/11
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40805 )
Change subject: mb/google/kahlee: Hold WLAN PCIe reset low at boot for mordin ......................................................................
Patch Set 11: Code-Review+2
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40805 )
Change subject: mb/google/kahlee: Hold WLAN PCIe reset low at boot for mordin ......................................................................
Patch Set 12:
(4 comments)
https://review.coreboot.org/c/coreboot/+/40805/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40805/1//COMMIT_MSG@7 PS1, Line 7: support Realtek RTL8822CE WLAN
Hold WLAN PCIe reset low at boot […]
Done
https://review.coreboot.org/c/coreboot/+/40805/9//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40805/9//COMMIT_MSG@7 PS9, Line 7: mainboard
Done
Done
https://review.coreboot.org/c/coreboot/+/40805/9//COMMIT_MSG@9 PS9, Line 9: fullful
Done
Done
https://review.coreboot.org/c/coreboot/+/40805/1/src/mainboard/google/kahlee... File src/mainboard/google/kahlee/variants/careena/variant.c:
https://review.coreboot.org/c/coreboot/+/40805/1/src/mainboard/google/kahlee... PS1, Line 40:
Hi Martin, […]
Done
Simon Glass has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40805 )
Change subject: mb/google/kahlee: Hold WLAN PCIe reset low at boot for mordin ......................................................................
Patch Set 12: Code-Review+2
Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40805 )
Change subject: mb/google/kahlee: Hold WLAN PCIe reset low at boot for mordin ......................................................................
mb/google/kahlee: Hold WLAN PCIe reset low at boot for mordin
gpio70 is assigned to use as WLAN rst in new schematic to fulfill RTK RTL8822CE power sequence: WLAN rst will need to be active at least 50ms after WLAN power on.
Also in order to keep the rst low in consistency, override default gpio70 to low.
BUG=b:154357210,b:154848243 BRANCH=master TEST=emerge-grunt coreboot
Change-Id: I98c8afe42b7f92016f83483acbb3b9ae64b159f7 Signed-off-by: Kevin Chiu Kevin.Chiu@quantatw.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/40805 Reviewed-by: Simon Glass sjg@chromium.org Reviewed-by: Martin Roth martinroth@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/kahlee/variants/careena/Makefile.inc M src/mainboard/google/kahlee/variants/careena/variant.c 2 files changed, 25 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Simon Glass: Looks good to me, approved
diff --git a/src/mainboard/google/kahlee/variants/careena/Makefile.inc b/src/mainboard/google/kahlee/variants/careena/Makefile.inc index dcd7d30..60da7f3 100644 --- a/src/mainboard/google/kahlee/variants/careena/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/careena/Makefile.inc @@ -6,6 +6,7 @@
subdirs-y += ./spd
+bootblock-y += variant.c romstage-y += variant.c
ramstage-y += ../baseboard/mainboard.c diff --git a/src/mainboard/google/kahlee/variants/careena/variant.c b/src/mainboard/google/kahlee/variants/careena/variant.c index e0bd5d1..e5a05ac 100644 --- a/src/mainboard/google/kahlee/variants/careena/variant.c +++ b/src/mainboard/google/kahlee/variants/careena/variant.c @@ -4,10 +4,24 @@ #include <ec/google/chromeec/ec.h> #include <baseboard/variants.h> #include <variant/sku.h> +#include <gpio.h> +#include <variant/gpio.h> + +static const struct soc_amd_gpio variant_gpio_wlan_rst_early_reset[] = { + /* GPIO_70 - WLAN_PE_RST_L */ + PAD_GPO(GPIO_70, LOW), +}; + +const struct soc_amd_gpio *variant_wlan_rst_early_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(variant_gpio_wlan_rst_early_reset); + return variant_gpio_wlan_rst_early_reset; +}
void variant_romstage_entry(int s3_resume) { uint32_t sku = google_chromeec_get_sku_id(); + uint32_t bid;
if (!s3_resume) { /* Based on SKU, turn on keyboard backlight */ @@ -23,4 +37,14 @@ break; } } + + google_chromeec_get_board_version(&bid); + + if (bid == 7) + /* + * Config WLAN RST - GPIO70 PU: release RST + * From RTK RTL8822CE spec, WLAN RST needs to be active + * at least 50 ms since WLAN power on + */ + gpio_set(GPIO_70, 1); }
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40805 )
Change subject: mb/google/kahlee: Hold WLAN PCIe reset low at boot for mordin ......................................................................
Patch Set 13:
Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/3295 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/3294 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/3293 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/3292
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
build bot (Jenkins) (Code Review)
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Kevin Chiu (Code Review)
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Martin Roth (Code Review)
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Paul Menzel (Code Review)
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Simon Glass (Code Review)