1) This would require an RO spin, which we're trying to avoid.
2) There's also an issue of the pcie reset which needs to be 6ms.

I think doing a hardware spin and an RO spin is a heavy-handed way to solve this, especially since I think we can solve it in RW by changing AGESA.

Can we leave this on hold for now?

Patch set 1:Code-Review -1

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I98c8afe42b7f92016f83483acbb3b9ae64b159f7
Gerrit-Change-Number: 40805
Gerrit-PatchSet: 1
Gerrit-Owner: Kevin Chiu <Kevin.Chiu@quantatw.com>
Gerrit-Reviewer: Martin Roth <martinroth@google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-Comment-Date: Tue, 28 Apr 2020 15:56:14 +0000
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