Change in ...coreboot[master]: mb/google/sarien: Swap FMAP location for RW_LEGACY and NVRAM

[Duncan Laurie (Code Review)]

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31436

Change subject: mb/google/sarien: Swap FMAP location for RW_LEGACY and NVRAM
......................................................................

mb/google/sarien: Swap FMAP location for RW_LEGACY and NVRAM

The Intel SOC can only shadow the top 16MB of SPI into memory so
in order to make it easier to access the NVRAM region with memory
mapped interface move it above the much larger RW_LEGACY region.

I tested to confirm that this region can now be read via MMIO
interface and does not need to use the hwseq SPI controller.

Change-Id: Iafacb01eec07beaf474b6a1f2b36a77117e327da
Signed-off-by: Duncan Laurie 
---
M src/mainboard/google/sarien/chromeos.fmd
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/31436/1

diff --git a/src/mainboard/google/sarien/chromeos.fmd b/src/mainboard/google/sarien/chromeos.fmd
index 2408a30..db0af0f 100644
--- a/src/mainboard/google/sarien/chromeos.fmd
+++ b/src/mainboard/google/sarien/chromeos.fmd
@@ -8,8 +8,8 @@
    }
    SI_BIOS@0x400000 0x1c00000 {
    	RW_DIAG@0x0 0x12d0000 {
-			DIAG_NVRAM@0x0 0x10000
-			RW_LEGACY(CBFS)@0x10000 0x12c0000
+			RW_LEGACY(CBFS)@0x0 0x12c0000
+			DIAG_NVRAM@0x12c0000 0x10000
    	}
    	RW_SECTION_A@0x12d0000 0x280000 {
    		VBLOCK_A@0x0 0x10000

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31436 )

Change subject: mb/google/sarien: Swap FMAP location for RW_LEGACY and NVRAM
......................................................................

Patch Set 1: Code-Review+2

[Lijian Zhao (Code Review)]

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31436 )

Change subject: mb/google/sarien: Swap FMAP location for RW_LEGACY and NVRAM
......................................................................

Patch Set 1: Code-Review+2

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31436 )

Change subject: mb/google/sarien: Swap FMAP location for RW_LEGACY and NVRAM
......................................................................

mb/google/sarien: Swap FMAP location for RW_LEGACY and NVRAM

The Intel SOC can only shadow the top 16MB of SPI into memory so
in order to make it easier to access the NVRAM region with memory
mapped interface move it above the much larger RW_LEGACY region.

I tested to confirm that this region can now be read via MMIO
interface and does not need to use the hwseq SPI controller.

Change-Id: Iafacb01eec07beaf474b6a1f2b36a77117e327da
Signed-off-by: Duncan Laurie 
Reviewed-on: https://review.coreboot.org/c/31436
Tested-by: build bot (Jenkins) 
Reviewed-by: Furquan Shaikh 
Reviewed-by: Lijian Zhao 
---
M src/mainboard/google/sarien/chromeos.fmd
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Lijian Zhao: Looks good to me, approved

diff --git a/src/mainboard/google/sarien/chromeos.fmd b/src/mainboard/google/sarien/chromeos.fmd
index 2408a30..db0af0f 100644
--- a/src/mainboard/google/sarien/chromeos.fmd
+++ b/src/mainboard/google/sarien/chromeos.fmd
@@ -8,8 +8,8 @@
    }
    SI_BIOS@0x400000 0x1c00000 {
    	RW_DIAG@0x0 0x12d0000 {
-			DIAG_NVRAM@0x0 0x10000
-			RW_LEGACY(CBFS)@0x10000 0x12c0000
+			RW_LEGACY(CBFS)@0x0 0x12c0000
+			DIAG_NVRAM@0x12c0000 0x10000
    	}
    	RW_SECTION_A@0x12d0000 0x280000 {
    		VBLOCK_A@0x0 0x10000