Duncan Laurie has uploaded this change for review.

View Change

mb/google/sarien: Swap FMAP location for RW_LEGACY and NVRAM

The Intel SOC can only shadow the top 16MB of SPI into memory so
in order to make it easier to access the NVRAM region with memory
mapped interface move it above the much larger RW_LEGACY region.

I tested to confirm that this region can now be read via MMIO
interface and does not need to use the hwseq SPI controller.

Change-Id: Iafacb01eec07beaf474b6a1f2b36a77117e327da
Signed-off-by: Duncan Laurie <dlaurie@google.com>
---
M src/mainboard/google/sarien/chromeos.fmd
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/31436/1

diff --git a/src/mainboard/google/sarien/chromeos.fmd b/src/mainboard/google/sarien/chromeos.fmd
index 2408a30..db0af0f 100644
--- a/src/mainboard/google/sarien/chromeos.fmd
+++ b/src/mainboard/google/sarien/chromeos.fmd
@@ -8,8 +8,8 @@
 	}
 	SI_BIOS@0x400000 0x1c00000 {
 		RW_DIAG@0x0 0x12d0000 {
-			DIAG_NVRAM@0x0 0x10000
-			RW_LEGACY(CBFS)@0x10000 0x12c0000
+			RW_LEGACY(CBFS)@0x0 0x12c0000
+			DIAG_NVRAM@0x12c0000 0x10000
 		}
 		RW_SECTION_A@0x12d0000 0x280000 {
 			VBLOCK_A@0x0 0x10000

To view, visit change 31436. To unsubscribe, or for help writing mail filters, visit settings.