Change in coreboot[master]: arch/riscv: Add SMP support for exception handling

[Xiang W (Code Review)]

Attention is currently required from: Philipp Hug, ron minnich.
Hello build bot (Jenkins), Philipp Hug, ron minnich,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/53944

to look at the new patch set (#3).

Change subject: arch/riscv: Add SMP support for exception handling
......................................................................

arch/riscv: Add SMP support for exception handling

The previous exception handling code does not support SMP. If start
Linux directly through coreboot, it will be a big problem.

Change-Id: Id8d3085bcd6f8883b08384f6bbf14052fd81fc2b
Signed-off-by: Xiang W 
---
M src/arch/riscv/bootblock.S
M src/arch/riscv/ramstage.S
M src/arch/riscv/trap_util.S
3 files changed, 17 insertions(+), 25 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/53944/3