Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44430 )
Change subject: cse_lite: Move global reset after MRC writeback.
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Patch Set 1: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/44430/1/src/soc/intel/common/block/...
File src/soc/intel/common/block/cse/cse_lite.c:
https://review.coreboot.org/c/coreboot/+/44430/1/src/soc/intel/common/block/...
PS1, Line 657: #if CONFIG(SOC_INTEL_TIGERLAKE)
It would be helpful to have a comment here explaining why this particular phase was chosen for Tigerlake. Once the MRC cache write is moved to happen early, this can be revisited.
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Gerrit-Project: coreboot
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Gerrit-Change-Id: Ia42d72fdec41f9792ab8f04205b20a55758a4235
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