Patch set 1:Code-Review +2

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1 comment:

• File src/soc/intel/common/block/cse/cse_lite.c:

  • Patch Set #1, Line 657: #if CONFIG(SOC_INTEL_TIGERLAKE)

    It would be helpful to have a comment here explaining why this particular phase was chosen for Tigerlake. Once the MRC cache write is moved to happen early, this can be revisited.

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