HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33504
Change subject: MSR: Move MSR_PLATFORM_INFO to common place ......................................................................
MSR: Move MSR_PLATFORM_INFO to common place
Change-Id: I45cd255e0af4369926a6cb884be9ee71bf1a66de Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/cpu/intel/fsp_model_406dx/model_406dx.h M src/cpu/intel/haswell/haswell.h M src/cpu/intel/model_2065x/model_2065x.h M src/cpu/intel/model_206ax/model_206ax.h M src/include/cpu/x86/msr.h M src/include/cpu/x86/tsc.h M src/soc/intel/baytrail/include/soc/msr.h M src/soc/intel/braswell/include/soc/msr.h M src/soc/intel/broadwell/include/soc/msr.h M src/soc/intel/common/block/include/intelblocks/msr.h M src/soc/intel/denverton_ns/include/soc/msr.h M src/soc/intel/fsp_baytrail/include/soc/msr.h M src/soc/intel/fsp_broadwell_de/include/soc/msr.h 13 files changed, 2 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/33504/1
diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx.h b/src/cpu/intel/fsp_model_406dx/model_406dx.h index 6c5cc31..4ee294f 100644 --- a/src/cpu/intel/fsp_model_406dx/model_406dx.h +++ b/src/cpu/intel/fsp_model_406dx/model_406dx.h @@ -30,8 +30,6 @@
#define MSR_NO_EVICT_MODE 0x2e0 #define MSR_PIC_MSG_CONTROL 0x2e -#define MSR_PLATFORM_INFO 0xce -#define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 4ebbe18..b7ce762 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -43,8 +43,6 @@ #define MSR_LT_LOCK_MEMORY 0x2e7
#define MSR_PIC_MSG_CONTROL 0x2e -#define MSR_PLATFORM_INFO 0xce -#define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4
diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index eab2dd5..cc830a9 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -30,8 +30,6 @@ #define FERR_ENABLE (1 << 0)
#define MSR_PIC_MSG_CONTROL 0x2e -#define MSR_PLATFORM_INFO 0xce -#define PLATFORM_INFO_SET_TDP (1 << 29)
#define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index c0d2434..795ab79 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -30,8 +30,6 @@ #define MSR_TEMPERATURE_TARGET 0x1a2 #define MSR_LT_LOCK_MEMORY 0x2e7 #define MSR_PIC_MSG_CONTROL 0x2e -#define MSR_PLATFORM_INFO 0xce -#define PLATFORM_INFO_SET_TDP (1 << 29)
#define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 8c558ce..a4657c5 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -25,9 +25,10 @@ #define CPUID_DCA (1 << 18) #define CPUID_AES (1 << 25) #define SGX_GLOBAL_ENABLE (1 << 18) -#define PLATFORM_INFO_SET_TDP (1 << 29) #define IA32_BIOS_UPDT_TRIG 0x79 #define IA32_BIOS_SIGN_ID 0x8b +#define MSR_PLATFORM_INFO 0xce +#define PLATFORM_INFO_SET_TDP (1 << 29) #define IA32_MPERF 0xe7 #define IA32_APERF 0xe8 #define IA32_MCG_CAP 0x179 diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h index 8dd9b75..dd333e8 100644 --- a/src/include/cpu/x86/tsc.h +++ b/src/include/cpu/x86/tsc.h @@ -11,8 +11,6 @@ #define TSC_SYNC #endif
-#define MSR_PLATFORM_INFO 0xce - struct tsc_struct { unsigned int lo; unsigned int hi; diff --git a/src/soc/intel/baytrail/include/soc/msr.h b/src/soc/intel/baytrail/include/soc/msr.h index e39758c..8b35355 100644 --- a/src/soc/intel/baytrail/include/soc/msr.h +++ b/src/soc/intel/baytrail/include/soc/msr.h @@ -17,7 +17,6 @@ #define _BAYTRAIL_MSR_H_
#define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd -#define MSR_PLATFORM_INFO 0xce #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define SINGLE_PCTL (1 << 11) #define MSR_POWER_MISC 0x120 diff --git a/src/soc/intel/braswell/include/soc/msr.h b/src/soc/intel/braswell/include/soc/msr.h index 6137820..a121180 100644 --- a/src/soc/intel/braswell/include/soc/msr.h +++ b/src/soc/intel/braswell/include/soc/msr.h @@ -18,7 +18,6 @@ #define _SOC_MSR_H_
#define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd -#define MSR_PLATFORM_INFO 0xce #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define SINGLE_PCTL (1 << 11) #define MSR_POWER_MISC 0x120 diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h index e8e3aa2..58dcba8 100644 --- a/src/soc/intel/broadwell/include/soc/msr.h +++ b/src/soc/intel/broadwell/include/soc/msr.h @@ -18,7 +18,6 @@
#define MSR_PIC_MSG_CONTROL 0x2e #define MSR_CORE_THREAD_COUNT 0x35 -#define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4 diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 6fdf26e..655b325 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -17,7 +17,6 @@ #define SOC_INTEL_COMMON_MSR_H
#define MSR_CORE_THREAD_COUNT 0x35 -#define MSR_PLATFORM_INFO 0xce #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 /* Set MSR_PKG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */ #define PKG_C_STATE_LIMIT_C2_MASK 0x2 diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h index 0d469c4..d63257b 100644 --- a/src/soc/intel/denverton_ns/include/soc/msr.h +++ b/src/soc/intel/denverton_ns/include/soc/msr.h @@ -20,7 +20,6 @@
#define MSR_PIC_MSG_CONTROL 0x2e #define MSR_CORE_THREAD_COUNT 0x35 -#define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4 diff --git a/src/soc/intel/fsp_baytrail/include/soc/msr.h b/src/soc/intel/fsp_baytrail/include/soc/msr.h index b8fe7fe..8ace3f6 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/msr.h +++ b/src/soc/intel/fsp_baytrail/include/soc/msr.h @@ -17,7 +17,6 @@ #define _BAYTRAIL_MSR_H_
#define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd -#define MSR_PLATFORM_INFO 0xce #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_POWER_MISC 0x120 #define MSR_POWER_CTL 0x1fc diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h index e4b8c50..6ae0bae 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h @@ -19,7 +19,6 @@ #define _SOC_MSR_H_
#define MSR_CORE_THREAD_COUNT 0x35 -#define MSR_PLATFORM_INFO 0xce #define MSR_TURBO_RATIO_LIMIT 0x1ad #define MSR_PKG_POWER_SKU_UNIT 0x606 #define MSR_PKG_POWER_LIMIT 0x610
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33504 )
Change subject: MSR: Move MSR_PLATFORM_INFO to common place ......................................................................
Patch Set 1: Code-Review+1
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33504 )
Change subject: MSR: Move MSR_PLATFORM_INFO to common place ......................................................................
Patch Set 1: Code-Review+1
Hello Kyösti Mälkki, Angel Pons, Patrick Rudolph, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33504
to look at the new patch set (#2).
Change subject: MSR: Move MSR_PLATFORM_INFO to common place ......................................................................
MSR: Move MSR_PLATFORM_INFO to common place
Change-Id: I45cd255e0af4369926a6cb884be9ee71bf1a66de Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/cpu/intel/fsp_model_406dx/model_406dx.h M src/cpu/intel/haswell/haswell.h M src/cpu/intel/model_2065x/model_2065x.h M src/cpu/intel/model_206ax/model_206ax.h M src/include/cpu/x86/msr.h M src/include/cpu/x86/tsc.h M src/soc/intel/baytrail/include/soc/msr.h M src/soc/intel/braswell/include/soc/msr.h M src/soc/intel/broadwell/include/soc/msr.h M src/soc/intel/common/block/include/intelblocks/msr.h M src/soc/intel/denverton_ns/include/soc/msr.h M src/soc/intel/fsp_baytrail/include/soc/msr.h M src/soc/intel/fsp_broadwell_de/include/soc/msr.h 13 files changed, 2 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/33504/2
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33504 )
Change subject: MSR: Move MSR_PLATFORM_INFO to common place ......................................................................
Patch Set 2: Code-Review-1
(1 comment)
https://review.coreboot.org/#/c/33504/2/src/include/cpu/x86/msr.h File src/include/cpu/x86/msr.h:
https://review.coreboot.org/#/c/33504/2/src/include/cpu/x86/msr.h@31 PS2, Line 31: #define PLATFORM_INFO_SET_TDP (1 << 29) The MSR in question is not architectural. It's not defined with this name even for all intel, thus it does not belong in a directory cpu/x86.
Hello Kyösti Mälkki, Angel Pons, Patrick Rudolph, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33504
to look at the new patch set (#3).
Change subject: MSR: Move common intel's MSRs to common place ......................................................................
MSR: Move common intel's MSRs to common place
New 'cpu/intel/msr.h' added for common intel's MSRs
Change-Id: I45cd255e0af4369926a6cb884be9ee71bf1a66de Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/cpu/intel/common/common_init.c M src/cpu/intel/fsp_model_406dx/acpi.c M src/cpu/intel/fsp_model_406dx/model_406dx.h M src/cpu/intel/fsp_model_406dx/model_406dx_init.c M src/cpu/intel/haswell/acpi.c M src/cpu/intel/haswell/bootblock.c M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/haswell/tsc_freq.c M src/cpu/intel/microcode/microcode.c M src/cpu/intel/microcode/microcode_asm.S M src/cpu/intel/model_1067x/model_1067x_init.c M src/cpu/intel/model_1067x/mp_init.c M src/cpu/intel/model_106cx/model_106cx_init.c M src/cpu/intel/model_2065x/acpi.c M src/cpu/intel/model_2065x/bootblock.c M src/cpu/intel/model_2065x/model_2065x.h M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/intel/model_2065x/tsc_freq.c M src/cpu/intel/model_206ax/acpi.c M src/cpu/intel/model_206ax/bootblock.c M src/cpu/intel/model_206ax/common.c M src/cpu/intel/model_206ax/model_206ax.h M src/cpu/intel/model_206ax/model_206ax_init.c M src/cpu/intel/model_206ax/tsc_freq.c M src/cpu/intel/model_6ex/model_6ex_init.c M src/cpu/intel/model_6fx/model_6fx_init.c M src/cpu/intel/slot_1/l2_cache.c M src/cpu/intel/smm/gen1/smmrelocate.c M src/cpu/intel/speedstep/speedstep.c M src/cpu/intel/turbo/turbo.c M src/cpu/via/nano/nano_init.c M src/cpu/via/nano/update_ucode.c M src/cpu/x86/sipi_vector.S A src/include/cpu/intel/msr.h M src/include/cpu/x86/msr.h M src/include/cpu/x86/tsc.h M src/mainboard/ocp/monolake/romstage.c M src/mainboard/ocp/wedge100s/romstage.c M src/northbridge/intel/fsp_rangeley/udelay.c M src/northbridge/intel/i945/udelay.c M src/northbridge/intel/nehalem/early_init.c M src/soc/intel/apollolake/cpu.c M src/soc/intel/baytrail/include/soc/msr.h M src/soc/intel/baytrail/ramstage.c M src/soc/intel/baytrail/tsc_freq.c M src/soc/intel/braswell/include/soc/msr.h M src/soc/intel/braswell/ramstage.c M src/soc/intel/braswell/tsc_freq.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/bootblock/cpu.c M src/soc/intel/broadwell/cpu.c M src/soc/intel/broadwell/include/soc/msr.h M src/soc/intel/broadwell/romstage/cpu.c M src/soc/intel/broadwell/tsc_freq.c M src/soc/intel/cannonlake/cpu.c M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/include/intelblocks/msr.h M src/soc/intel/common/block/sgx/sgx.c M src/soc/intel/denverton_ns/cpu.c M src/soc/intel/denverton_ns/include/soc/msr.h M src/soc/intel/denverton_ns/tsc_freq.c M src/soc/intel/fsp_baytrail/include/soc/msr.h M src/soc/intel/fsp_baytrail/ramstage.c M src/soc/intel/fsp_baytrail/romstage/report_platform.c M src/soc/intel/fsp_baytrail/tsc_freq.c M src/soc/intel/fsp_broadwell_de/acpi.c M src/soc/intel/fsp_broadwell_de/cpu.c M src/soc/intel/fsp_broadwell_de/include/soc/msr.h M src/soc/intel/fsp_broadwell_de/ramstage.c M src/soc/intel/fsp_broadwell_de/tsc_freq.c M src/soc/intel/icelake/cpu.c M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/cpu.c 74 files changed, 112 insertions(+), 49 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/33504/3
Hello Kyösti Mälkki, Angel Pons, Patrick Rudolph, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33504
to look at the new patch set (#4).
Change subject: MSR: Move common intel's MSRs to common place ......................................................................
MSR: Move common intel's MSRs to common place
New 'cpu/intel/msr.h' added for common intel's MSRs
Change-Id: I45cd255e0af4369926a6cb884be9ee71bf1a66de Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/cpu/intel/common/common_init.c M src/cpu/intel/fsp_model_406dx/acpi.c M src/cpu/intel/fsp_model_406dx/model_406dx.h M src/cpu/intel/fsp_model_406dx/model_406dx_init.c M src/cpu/intel/haswell/acpi.c M src/cpu/intel/haswell/bootblock.c M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/haswell/tsc_freq.c M src/cpu/intel/microcode/microcode.c M src/cpu/intel/microcode/microcode_asm.S M src/cpu/intel/model_1067x/model_1067x_init.c M src/cpu/intel/model_1067x/mp_init.c M src/cpu/intel/model_106cx/model_106cx_init.c M src/cpu/intel/model_2065x/acpi.c M src/cpu/intel/model_2065x/bootblock.c M src/cpu/intel/model_2065x/model_2065x.h M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/intel/model_2065x/tsc_freq.c M src/cpu/intel/model_206ax/acpi.c M src/cpu/intel/model_206ax/bootblock.c M src/cpu/intel/model_206ax/common.c M src/cpu/intel/model_206ax/model_206ax.h M src/cpu/intel/model_206ax/model_206ax_init.c M src/cpu/intel/model_206ax/tsc_freq.c M src/cpu/intel/model_6ex/model_6ex_init.c M src/cpu/intel/model_6fx/model_6fx_init.c M src/cpu/intel/slot_1/l2_cache.c M src/cpu/intel/smm/gen1/smmrelocate.c M src/cpu/intel/speedstep/speedstep.c M src/cpu/intel/turbo/turbo.c M src/cpu/via/nano/nano_init.c M src/cpu/via/nano/update_ucode.c M src/cpu/x86/sipi_vector.S A src/include/cpu/intel/msr.h M src/include/cpu/x86/msr.h M src/include/cpu/x86/tsc.h M src/mainboard/ocp/monolake/romstage.c M src/mainboard/ocp/wedge100s/romstage.c M src/northbridge/intel/fsp_rangeley/udelay.c M src/northbridge/intel/i945/udelay.c M src/northbridge/intel/nehalem/early_init.c M src/soc/intel/apollolake/cpu.c M src/soc/intel/baytrail/include/soc/msr.h M src/soc/intel/baytrail/ramstage.c M src/soc/intel/baytrail/tsc_freq.c M src/soc/intel/braswell/include/soc/msr.h M src/soc/intel/braswell/ramstage.c M src/soc/intel/braswell/tsc_freq.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/bootblock/cpu.c M src/soc/intel/broadwell/cpu.c M src/soc/intel/broadwell/include/soc/msr.h M src/soc/intel/broadwell/romstage/cpu.c M src/soc/intel/broadwell/tsc_freq.c M src/soc/intel/cannonlake/cpu.c M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/cpu/car/exit_car.S M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/include/intelblocks/msr.h M src/soc/intel/common/block/sgx/sgx.c M src/soc/intel/denverton_ns/cpu.c M src/soc/intel/denverton_ns/include/soc/msr.h M src/soc/intel/denverton_ns/tsc_freq.c M src/soc/intel/fsp_baytrail/include/soc/msr.h M src/soc/intel/fsp_baytrail/ramstage.c M src/soc/intel/fsp_baytrail/romstage/report_platform.c M src/soc/intel/fsp_baytrail/tsc_freq.c M src/soc/intel/fsp_broadwell_de/acpi.c M src/soc/intel/fsp_broadwell_de/cpu.c M src/soc/intel/fsp_broadwell_de/include/soc/msr.h M src/soc/intel/fsp_broadwell_de/ramstage.c M src/soc/intel/fsp_broadwell_de/tsc_freq.c M src/soc/intel/icelake/cpu.c M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/cpu.c 76 files changed, 114 insertions(+), 49 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/33504/4
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33504 )
Change subject: MSR: Move common intel's MSRs to common place ......................................................................
Patch Set 4:
(1 comment)
FYI: I see little value here and wont be doing any proper review.
You should not push MSR register definitions that do not apply to all intel CPU models into a common file cpu/intel/msr.h.
https://review.coreboot.org/#/c/33504/4/src/include/cpu/intel/msr.h File src/include/cpu/intel/msr.h:
https://review.coreboot.org/#/c/33504/4/src/include/cpu/intel/msr.h@20 PS4, Line 20: #define MSR_PLATFORM_INFO 0xce This, for example, is not defined for all Intel models.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33504 )
Change subject: MSR: Move common intel's MSRs to common place ......................................................................
Patch Set 4: Code-Review-1
Patch Set 4:
(1 comment)
FYI: I see little value here and wont be doing any proper review.
You should not push MSR register definitions that do not apply to all intel CPU models into a common file cpu/intel/msr.h.
I agree. MSR stands for Model-Specific Register. I would rather have the same register definition in a dozen different files, so that one knows what MSRs exist for a certain CPU model (the code also acts as documentation).
Having a single definition on a common file is very likely to cause confusion: "Does this MSR exist for *my* chip?"
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33504 )
Change subject: MSR: Move common intel's MSRs to common place ......................................................................
Patch Set 4:
Patch Set 4: Code-Review-1
Patch Set 4:
(1 comment)
FYI: I see little value here and wont be doing any proper review.
You should not push MSR register definitions that do not apply to all intel CPU models into a common file cpu/intel/msr.h.
I agree. MSR stands for Model-Specific Register. I would rather have the same register definition in a dozen different files, so that one knows what MSRs exist for a certain CPU model (the code also acts as documentation).
As ~95% of all definitions are copy pasta, you can't rely on these anyway. If we had the resources to review / cleanup the mess of silicon vendors, I would agree. But as long as we don't, I would prefer a practice that avoids copy pasta.
Having a single definition on a common file is very likely to cause confusion: "Does this MSR exist for *my* chip?"
Does it start with IA32_? then yes. Does it start with MSR_? then check documentation.
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33504 )
Change subject: MSR: Move common intel's MSRs to common place ......................................................................
Patch Set 4:
(2 comments)
not easy task .... we have: - x86/amd64 common MSRs - some common intel's MSRs - platform's specific MSRs (for intel) - AMD seems to be ok (probably if we remove "I32_" from x86/64 MSRs)
https://review.coreboot.org/c/coreboot/+/33504/4/src/include/cpu/x86/msr.h File src/include/cpu/x86/msr.h:
https://review.coreboot.org/c/coreboot/+/33504/4/src/include/cpu/x86/msr.h@1... PS4, Line 19: FEATURE_CONTROL_LOCK_BIT (1 << 0) : #define FEATURE_ENABLE_VMX (1 << 2) : #define SMRR_ENABLE (1 << 3) : #define CPUID_VMX (1 << 5) : #define CPUID_SMX (1 << 6) linked to IA32_FEATURE_CONTROL
https://review.coreboot.org/c/coreboot/+/33504/4/src/include/cpu/x86/msr.h@2... PS4, Line 24: CPUID_DCA (1 << 18) this is for IA32_PLATFORM_DCA_CAP
HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/33504 )
Change subject: MSR: Move common intel's MSRs to common place ......................................................................
Abandoned
-
Angel Pons (Code Review) -
HAOUAS Elyes (Code Review)
-
Kyösti Mälkki (Code Review)
-
Nico Huber (Code Review)
-
Paul Menzel (Code Review)