Change in coreboot[master]: soc/intel/skylake: Configure L1 substates for PCH root ports

[Nico Huber (Code Review)]

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39538 )

Change subject: soc/intel/skylake: Configure L1 substates for PCH root ports
......................................................................

soc/intel/skylake: Configure L1 substates for PCH root ports

Exposes PcieRpL1Substates to devicetree to allow boards to override this configuration.

Tested on an Acer Aspire VN7-572G (Skylake-U).

Change-Id: I36150858485715016158595c832c142b0582ddb8
Signed-off-by: Benjamin Doron 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39538
Tested-by: build bot (Jenkins) 
Reviewed-by: Nico Huber 
---
M src/soc/intel/skylake/chip.c
M src/soc/intel/skylake/chip.h
2 files changed, 10 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved

diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index dfbdfb8..4139570 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -212,6 +212,8 @@
    	params->PcieRpMaxPayload[i] = config->PcieRpMaxPayload[i];
    	if (config->PcieRpAspm[i])
    		params->PcieRpAspm[i] = config->PcieRpAspm[i] - 1;
+		if (config->pcie_rp_l1substates[i])
+			params->PcieRpL1Substates[i] = config->pcie_rp_l1substates[i] - 1;
    }

/*
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index fa30c1d..5befb01 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -264,6 +264,14 @@
    	AspmAutoConfig,
    } PcieRpAspm[CONFIG_MAX_ROOT_PORTS];

+	/* PCIe RP L1 substate */
+	enum {
+		L1SS_Default,
+		L1SS_Disabled,
+		L1SS_L1_1,
+		L1SS_L1_2,
+	} pcie_rp_l1substates[CONFIG_MAX_ROOT_PORTS];
+
    /* USB related */
    struct usb2_port_config usb2_ports[16];
    struct usb3_port_config usb3_ports[10];