Nico Huber submitted this change.
soc/intel/skylake: Configure L1 substates for PCH root ports
Exposes PcieRpL1Substates to devicetree to allow boards to override this configuration.
Tested on an Acer Aspire VN7-572G (Skylake-U).
Change-Id: I36150858485715016158595c832c142b0582ddb8
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
---
M src/soc/intel/skylake/chip.c
M src/soc/intel/skylake/chip.h
2 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index dfbdfb8..4139570 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -212,6 +212,8 @@
params->PcieRpMaxPayload[i] = config->PcieRpMaxPayload[i];
if (config->PcieRpAspm[i])
params->PcieRpAspm[i] = config->PcieRpAspm[i] - 1;
+ if (config->pcie_rp_l1substates[i])
+ params->PcieRpL1Substates[i] = config->pcie_rp_l1substates[i] - 1;
}
/*
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index fa30c1d..5befb01 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -264,6 +264,14 @@
AspmAutoConfig,
} PcieRpAspm[CONFIG_MAX_ROOT_PORTS];
+ /* PCIe RP L1 substate */
+ enum {
+ L1SS_Default,
+ L1SS_Disabled,
+ L1SS_L1_1,
+ L1SS_L1_2,
+ } pcie_rp_l1substates[CONFIG_MAX_ROOT_PORTS];
+
/* USB related */
struct usb2_port_config usb2_ports[16];
struct usb3_port_config usb3_ports[10];
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