Change in coreboot[master]: cpu/intel/socket_FCBGA559/Makefile.inc: Order entries

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44222 )

Change subject: cpu/intel/socket_FCBGA559/Makefile.inc: Order entries
......................................................................

cpu/intel/socket_FCBGA559/Makefile.inc: Order entries

Group lines by stages, then subdirs, then microcode. Within groups,
order in ascending count of `../` in prefix and then alphabetically.
Group CPU models separately from other subdirs, as they are special.

Tested with BUILD_TIMELESS=1, Foxconn D41S remains identical.

Change-Id: I5e95e609dcbf97a9448299171262ed6499686f73
Signed-off-by: Angel Pons 
---
M src/cpu/intel/socket_FCBGA559/Makefile.inc
1 file changed, 12 insertions(+), 11 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/44222/1

diff --git a/src/cpu/intel/socket_FCBGA559/Makefile.inc b/src/cpu/intel/socket_FCBGA559/Makefile.inc
index c95e135..08f88b6 100644
--- a/src/cpu/intel/socket_FCBGA559/Makefile.inc
+++ b/src/cpu/intel/socket_FCBGA559/Makefile.inc
@@ -1,16 +1,17 @@
-subdirs-y += ../model_106cx
-subdirs-y += ../../x86/tsc
-subdirs-y += ../../x86/mtrr
-subdirs-y += ../../x86/lapic
-subdirs-y += ../../x86/cache
-subdirs-y += ../../x86/smm
-subdirs-y += ../microcode
-subdirs-y += ../hyperthreading
-subdirs-y += ../speedstep
-
 bootblock-y += ../car/bootblock.c
 bootblock-y += ../car/non-evict/cache_as_ram.S

+romstage-y += ../car/romstage.c
+
 postcar-y += ../car/non-evict/exit_car.S

-romstage-y += ../car/romstage.c
+subdirs-y += ../model_106cx
+
+subdirs-y += ../hyperthreading
+subdirs-y += ../microcode
+subdirs-y += ../speedstep
+subdirs-y += ../../x86/cache
+subdirs-y += ../../x86/lapic
+subdirs-y += ../../x86/mtrr
+subdirs-y += ../../x86/smm
+subdirs-y += ../../x86/tsc

[Angel Pons (Code Review)]

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/44222

to look at the new patch set (#3).

Change subject: cpu/intel/socket_FCBGA559/Makefile.inc: Order entries
......................................................................

cpu/intel/socket_FCBGA559/Makefile.inc: Order entries

Group lines by stages, then subdirs, then microcode. Within groups,
order in ascending count of `../` in prefix and then alphabetically.
Group CPU models separately from other subdirs, as they are special.

Tested with BUILD_TIMELESS=1, Foxconn D41S remains identical.

Change-Id: I5e95e609dcbf97a9448299171262ed6499686f73
Signed-off-by: Angel Pons 
---
M src/cpu/intel/socket_FCBGA559/Makefile.inc
1 file changed, 12 insertions(+), 11 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/44222/3

[Angel Pons (Code Review)]

Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/44222 )

Change subject: cpu/intel/socket_FCBGA559/Makefile.inc: Order entries
......................................................................

Abandoned

Sorry, I ran out of patience and energy to care about these changes any longer.