Change in coreboot[master]: riscv: Implement ipi using clint for emulation to enable smp in qemu.
Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35246 )
Change subject: riscv: Implement ipi using clint for emulation to enable smp in qemu. ......................................................................
riscv: Implement ipi using clint for emulation to enable smp in qemu.
testing=Set MAX_CPUS=2 and run qemu with -smp 2
Change-Id: I94fb25fad103e3cb5db676eb4caead11d54ae0ae --- M src/mainboard/emulation/qemu-riscv/Makefile.inc M src/mainboard/emulation/qemu-riscv/clint.c M src/mainboard/emulation/spike-riscv/Makefile.inc M src/mainboard/emulation/spike-riscv/clint.c M src/soc/ucb/riscv/Makefile.inc D src/soc/ucb/riscv/ipi.c 6 files changed, 14 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/35246/1
diff --git a/src/mainboard/emulation/qemu-riscv/Makefile.inc b/src/mainboard/emulation/qemu-riscv/Makefile.inc index eb99544..2ca75fd 100644 --- a/src/mainboard/emulation/qemu-riscv/Makefile.inc +++ b/src/mainboard/emulation/qemu-riscv/Makefile.inc @@ -19,6 +19,7 @@ romstage-y += romstage.c romstage-y += uart.c romstage-y += rom_media.c +romstage-y += clint.c
ramstage-y += uart.c ramstage-y += rom_media.c diff --git a/src/mainboard/emulation/qemu-riscv/clint.c b/src/mainboard/emulation/qemu-riscv/clint.c index 367d48d..4a00bc2 100644 --- a/src/mainboard/emulation/qemu-riscv/clint.c +++ b/src/mainboard/emulation/qemu-riscv/clint.c @@ -14,6 +14,7 @@ */
#include <mcall.h> +#include <device/mmio.h> #include <mainboard/addressmap.h>
/* This function is used to initialize HLS()->time/HLS()->timecmp */ @@ -23,3 +24,8 @@ HLS()->time = (uint64_t *)(QEMU_VIRT_CLINT + 0xbff8); HLS()->timecmp = (uint64_t *)(QEMU_VIRT_CLINT + 0x4000 + 8 * hart_id); } + +void set_msip(int hartid, int val) +{ + write32((void *)(QEMU_VIRT_CLINT + 4 * (uintptr_t)hartid), !!val); +} diff --git a/src/mainboard/emulation/spike-riscv/Makefile.inc b/src/mainboard/emulation/spike-riscv/Makefile.inc index 38977b6..bfeaf58 100644 --- a/src/mainboard/emulation/spike-riscv/Makefile.inc +++ b/src/mainboard/emulation/spike-riscv/Makefile.inc @@ -18,6 +18,7 @@ romstage-y += romstage.c romstage-y += uart.c romstage-y += rom_media.c +romstage-y += clint.c ramstage-y += uart.c ramstage-y += rom_media.c ramstage-y += clint.c diff --git a/src/mainboard/emulation/spike-riscv/clint.c b/src/mainboard/emulation/spike-riscv/clint.c index 7ad3f5a..c39e058 100644 --- a/src/mainboard/emulation/spike-riscv/clint.c +++ b/src/mainboard/emulation/spike-riscv/clint.c @@ -14,6 +14,7 @@ */
#include <mcall.h> +#include <device/mmio.h>
#define SPIKE_CLINT_BASE 0x02000000
@@ -24,3 +25,8 @@ HLS()->time = (uint64_t *)(SPIKE_CLINT_BASE + 0xbff8); HLS()->timecmp = (uint64_t *)(SPIKE_CLINT_BASE + 0x4000 + 8 * hart_id); } + +void set_msip(int hartid, int val) +{ + write32((void *)(SPIKE_CLINT_BASE + 4 * (uintptr_t)hartid), !!val); +} diff --git a/src/soc/ucb/riscv/Makefile.inc b/src/soc/ucb/riscv/Makefile.inc index ef03642..80899d57 100644 --- a/src/soc/ucb/riscv/Makefile.inc +++ b/src/soc/ucb/riscv/Makefile.inc @@ -1,11 +1,7 @@ ifeq ($(CONFIG_SOC_UCB_RISCV),y)
-bootblock-y += ipi.c - romstage-y += cbmem.c -romstage-y += ipi.c
ramstage-y += cbmem.c -ramstage-y += ipi.c
endif diff --git a/src/soc/ucb/riscv/ipi.c b/src/soc/ucb/riscv/ipi.c deleted file mode 100644 index 80307a8..0000000 --- a/src/soc/ucb/riscv/ipi.c +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 HardenedLinux - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <mcall.h> - -/* TODO: Please implement this function */ -void set_msip(int hartid, int val) -{ -}
Hello ron minnich, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35246
to look at the new patch set (#2).
Change subject: mb/emulation/qemu-riscv: Implement ipi using clint to enable smp in qemu/spike. ......................................................................
mb/emulation/qemu-riscv: Implement ipi using clint to enable smp in qemu/spike.
testing=Set MAX_CPUS=2 and run qemu with -smp 2
Change-Id: I94fb25fad103e3cb5db676eb4caead11d54ae0ae --- M src/mainboard/emulation/qemu-riscv/Makefile.inc M src/mainboard/emulation/qemu-riscv/clint.c M src/mainboard/emulation/spike-riscv/Makefile.inc M src/mainboard/emulation/spike-riscv/clint.c M src/soc/ucb/riscv/Makefile.inc D src/soc/ucb/riscv/ipi.c 6 files changed, 14 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/35246/2
Hello ron minnich, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35246
to look at the new patch set (#3).
Change subject: mb/emulation/qemu-riscv: Implement ipi using clint to enable smp in qemu/spike. ......................................................................
mb/emulation/qemu-riscv: Implement ipi using clint to enable smp in qemu/spike.
TEST=Set MAX_CPUS=2 and run qemu with -smp 2
Signed-off-by: Philipp Hug philipp@hug.cx Change-Id: I94fb25fad103e3cb5db676eb4caead11d54ae0ae --- M src/mainboard/emulation/qemu-riscv/Makefile.inc M src/mainboard/emulation/qemu-riscv/clint.c M src/mainboard/emulation/spike-riscv/Makefile.inc M src/mainboard/emulation/spike-riscv/clint.c M src/soc/ucb/riscv/Makefile.inc D src/soc/ucb/riscv/ipi.c 6 files changed, 14 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/35246/3
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35246 )
Change subject: mb/emulation/qemu-riscv: Implement ipi using clint to enable smp in qemu/spike. ......................................................................
Patch Set 3: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/35246/3/src/mainboard/emulation/spi... File src/mainboard/emulation/spike-riscv/clint.c:
https://review.coreboot.org/c/coreboot/+/35246/3/src/mainboard/emulation/spi... PS3, Line 31: write32((void *)(SPIKE_CLINT_BASE + 4 * (uintptr_t)hartid), !!val); the uintptr_t confused me, is it necessary?
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35246 )
Change subject: mb/emulation/qemu-riscv: Implement ipi using clint to enable smp in qemu/spike. ......................................................................
Patch Set 3: Code-Review-1
Tested on qemu: It hangs with MAX_CPUS=2 and -smp 1.
Philipp Hug has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35246 )
Change subject: mb/emulation/qemu-riscv: Implement ipi using clint to enable smp in qemu/spike. ......................................................................
Patch Set 3:
Patch Set 3: Code-Review-1
Tested on qemu: It hangs with MAX_CPUS=2 and -smp 1.
This is unrelated and needs to be addressed separately. The current riscv code waits for MAX_CPUS to be ready before it proceeds to the next stage. This should be changed into a timeout.
Philipp Hug has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35246 )
Change subject: mb/emulation/qemu-riscv: Implement ipi using clint to enable smp in qemu/spike. ......................................................................
Patch Set 3:
Patch Set 3: Code-Review+1
(1 comment)
yes it is necessary: src/mainboard/emulation/qemu-riscv/clint.c:30:10: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast]
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35246 )
Change subject: mb/emulation/qemu-riscv: Implement ipi using clint to enable smp in qemu/spike. ......................................................................
Patch Set 3:
Patch Set 3:
Patch Set 3: Code-Review-1
Tested on qemu: It hangs with MAX_CPUS=2 and -smp 1.
This is unrelated and needs to be addressed separately. The current riscv code waits for MAX_CPUS to be ready before it proceeds to the next stage. This should be changed into a timeout.
Please add that to the commit message. I'd detect the core count somehow at runtime instead of using MAX_CPUS.
Hello Patrick Rudolph, ron minnich, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35246
to look at the new patch set (#5).
Change subject: mb/emulation/qemu-riscv: Implement ipi using clint to enable smp in qemu/spike. ......................................................................
mb/emulation/qemu-riscv: Implement ipi using clint to enable smp in qemu/spike.
TEST=Set MAX_CPUS=2 and run qemu with -smp 2
Signed-off-by: Philipp Hug philipp@hug.cx Change-Id: I94fb25fad103e3cb5db676eb4caead11d54ae0ae --- M src/mainboard/emulation/qemu-riscv/Makefile.inc M src/mainboard/emulation/qemu-riscv/clint.c M src/mainboard/emulation/spike-riscv/Makefile.inc M src/mainboard/emulation/spike-riscv/clint.c M src/soc/ucb/riscv/Makefile.inc D src/soc/ucb/riscv/ipi.c 6 files changed, 14 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/35246/5
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35246 )
Change subject: mb/emulation/qemu-riscv: Implement ipi using clint to enable smp in qemu/spike. ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35246/3/src/mainboard/emulation/spi... File src/mainboard/emulation/spike-riscv/clint.c:
https://review.coreboot.org/c/coreboot/+/35246/3/src/mainboard/emulation/spi... PS3, Line 31: write32((void *)(SPIKE_CLINT_BASE + 4 * (uintptr_t)hartid), !!val);
the uintptr_t confused me, is it necessary?
Ack
Philipp Hug has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35246 )
Change subject: mb/emulation/qemu-riscv: Implement ipi using clint to enable smp in qemu/spike. ......................................................................
Patch Set 5:
Patch Set 5:
(1 comment)
Can you also remove the -1?
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35246 )
Change subject: mb/emulation/qemu-riscv: Implement ipi using clint to enable smp in qemu/spike. ......................................................................
Patch Set 5: -Code-Review
The runtime Hart detection is still missing.
Philipp Hug has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35246 )
Change subject: mb/emulation/qemu-riscv: Implement ipi using clint to enable smp in qemu/spike. ......................................................................
Patch Set 5:
Patch Set 5: -Code-Review
The runtime Hart detection is still missing.
Correct, harts should be detected instead of configured. But that requires a separate patch.
Xiang Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35246 )
Change subject: mb/emulation/qemu-riscv: Implement ipi using clint to enable smp in qemu/spike. ......................................................................
Patch Set 5: Code-Review+2
Looks good to me.
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35246 )
Change subject: mb/emulation/qemu-riscv: Implement ipi using clint to enable smp in qemu/spike. ......................................................................
mb/emulation/qemu-riscv: Implement ipi using clint to enable smp in qemu/spike.
TEST=Set MAX_CPUS=2 and run qemu with -smp 2
Signed-off-by: Philipp Hug philipp@hug.cx Change-Id: I94fb25fad103e3cb5db676eb4caead11d54ae0ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/35246 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Xiang Wang merle@hardenedlinux.org --- M src/mainboard/emulation/qemu-riscv/Makefile.inc M src/mainboard/emulation/qemu-riscv/clint.c M src/mainboard/emulation/spike-riscv/Makefile.inc M src/mainboard/emulation/spike-riscv/clint.c M src/soc/ucb/riscv/Makefile.inc D src/soc/ucb/riscv/ipi.c 6 files changed, 14 insertions(+), 25 deletions(-)
Approvals: build bot (Jenkins): Verified Xiang Wang: Looks good to me, approved
diff --git a/src/mainboard/emulation/qemu-riscv/Makefile.inc b/src/mainboard/emulation/qemu-riscv/Makefile.inc index eb99544..2ca75fd 100644 --- a/src/mainboard/emulation/qemu-riscv/Makefile.inc +++ b/src/mainboard/emulation/qemu-riscv/Makefile.inc @@ -19,6 +19,7 @@ romstage-y += romstage.c romstage-y += uart.c romstage-y += rom_media.c +romstage-y += clint.c
ramstage-y += uart.c ramstage-y += rom_media.c diff --git a/src/mainboard/emulation/qemu-riscv/clint.c b/src/mainboard/emulation/qemu-riscv/clint.c index 367d48d..4a00bc2 100644 --- a/src/mainboard/emulation/qemu-riscv/clint.c +++ b/src/mainboard/emulation/qemu-riscv/clint.c @@ -14,6 +14,7 @@ */
#include <mcall.h> +#include <device/mmio.h> #include <mainboard/addressmap.h>
/* This function is used to initialize HLS()->time/HLS()->timecmp */ @@ -23,3 +24,8 @@ HLS()->time = (uint64_t *)(QEMU_VIRT_CLINT + 0xbff8); HLS()->timecmp = (uint64_t *)(QEMU_VIRT_CLINT + 0x4000 + 8 * hart_id); } + +void set_msip(int hartid, int val) +{ + write32((void *)(QEMU_VIRT_CLINT + 4 * (uintptr_t)hartid), !!val); +} diff --git a/src/mainboard/emulation/spike-riscv/Makefile.inc b/src/mainboard/emulation/spike-riscv/Makefile.inc index 38977b6..bfeaf58 100644 --- a/src/mainboard/emulation/spike-riscv/Makefile.inc +++ b/src/mainboard/emulation/spike-riscv/Makefile.inc @@ -18,6 +18,7 @@ romstage-y += romstage.c romstage-y += uart.c romstage-y += rom_media.c +romstage-y += clint.c ramstage-y += uart.c ramstage-y += rom_media.c ramstage-y += clint.c diff --git a/src/mainboard/emulation/spike-riscv/clint.c b/src/mainboard/emulation/spike-riscv/clint.c index 7ad3f5a..c39e058 100644 --- a/src/mainboard/emulation/spike-riscv/clint.c +++ b/src/mainboard/emulation/spike-riscv/clint.c @@ -14,6 +14,7 @@ */
#include <mcall.h> +#include <device/mmio.h>
#define SPIKE_CLINT_BASE 0x02000000
@@ -24,3 +25,8 @@ HLS()->time = (uint64_t *)(SPIKE_CLINT_BASE + 0xbff8); HLS()->timecmp = (uint64_t *)(SPIKE_CLINT_BASE + 0x4000 + 8 * hart_id); } + +void set_msip(int hartid, int val) +{ + write32((void *)(SPIKE_CLINT_BASE + 4 * (uintptr_t)hartid), !!val); +} diff --git a/src/soc/ucb/riscv/Makefile.inc b/src/soc/ucb/riscv/Makefile.inc index ef03642..80899d57 100644 --- a/src/soc/ucb/riscv/Makefile.inc +++ b/src/soc/ucb/riscv/Makefile.inc @@ -1,11 +1,7 @@ ifeq ($(CONFIG_SOC_UCB_RISCV),y)
-bootblock-y += ipi.c - romstage-y += cbmem.c -romstage-y += ipi.c
ramstage-y += cbmem.c -ramstage-y += ipi.c
endif diff --git a/src/soc/ucb/riscv/ipi.c b/src/soc/ucb/riscv/ipi.c deleted file mode 100644 index 80307a8..0000000 --- a/src/soc/ucb/riscv/ipi.c +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 HardenedLinux - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <mcall.h> - -/* TODO: Please implement this function */ -void set_msip(int hartid, int val) -{ -}
-
Patrick Georgi (Code Review) -
Patrick Rudolph (Code Review)
-
Philipp Hug (Code Review)
-
Xiang Wang (Code Review)