Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41519 )
Change subject: soc/intel/common/block/acpi: Fix error in shift operation for GPCL ......................................................................
soc/intel/common/block/acpi: Fix error in shift operation for GPCL
CB:41454 updated northbridge.asl to ASL2.0 syntax. During this, GPCL was incorrectly updated to use << (ShiftLeft) instead of >> (ShiftRight). This change fixes the error in GPCL by updating it to use >> (ShiftRight).
Change-Id: I36469cb3b0bcc595acf0e43808d6a574986cad68 Signed-off-by: Furquan Shaikh furquan@google.com --- M src/soc/intel/common/block/acpi/acpi/northbridge.asl 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/41519/1
diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl index 53b2188..2d33ce3 100644 --- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl +++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl @@ -236,7 +236,7 @@ /* Get DMI BAR */ Method (GDMB, 0, Serialized) { - Local0 = _SB.PCI0.MCHC.DIBR << 12 + Local0 = _SB.PCI0.MCHC.DIBR >> 12 Return (Local0) }
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41519 )
Change subject: soc/intel/common/block/acpi: Fix error in shift operation for GPCL ......................................................................
Patch Set 1: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41519 )
Change subject: soc/intel/common/block/acpi: Fix error in shift operation for GPCL ......................................................................
Patch Set 1: Code-Review+2
Oops
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41519 )
Change subject: soc/intel/common/block/acpi: Fix error in shift operation for GPCL ......................................................................
Patch Set 1: Code-Review-1
(1 comment)
https://review.coreboot.org/c/coreboot/+/41519/1/src/soc/intel/common/block/... File src/soc/intel/common/block/acpi/acpi/northbridge.asl:
https://review.coreboot.org/c/coreboot/+/41519/1/src/soc/intel/common/block/... PS1, Line 232: << No, it's this one
Hello build bot (Jenkins), Duncan Laurie, Angel Pons, Aaron Durbin, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41519
to look at the new patch set (#2).
Change subject: soc/intel/common/block/acpi: Fix error in shift operation for GPCL ......................................................................
soc/intel/common/block/acpi: Fix error in shift operation for GPCL
CB:41454 updated northbridge.asl to ASL2.0 syntax. During this, GPCL was incorrectly updated to use << (ShiftLeft) instead of >> (ShiftRight). This change fixes the error in GPCL by updating it to use >> (ShiftRight).
Change-Id: I36469cb3b0bcc595acf0e43808d6a574986cad68 Signed-off-by: Furquan Shaikh furquan@google.com --- M src/soc/intel/common/block/acpi/acpi/northbridge.asl 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/41519/2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41519 )
Change subject: soc/intel/common/block/acpi: Fix error in shift operation for GPCL ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41519/1/src/soc/intel/common/block/... File src/soc/intel/common/block/acpi/acpi/northbridge.asl:
https://review.coreboot.org/c/coreboot/+/41519/1/src/soc/intel/common/block/... PS1, Line 232: <<
No, it's this one
Done
Hello build bot (Jenkins), Duncan Laurie, Angel Pons, Aaron Durbin, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41519
to look at the new patch set (#3).
Change subject: soc/intel/common/block/acpi: Fix error in shift operation for GPCL ......................................................................
soc/intel/common/block/acpi: Fix error in shift operation for GPCL
CB:41454 updated northbridge.asl to ASL2.0 syntax. During this, GPCL was incorrectly updated to use << (ShiftLeft) instead of >> (ShiftRight). This change fixes the error in GPCL by updating it to use >> (ShiftRight).
TEST=Verified using --timeless option to abuild that the resulting coreboot.rom is same as without the ASL2.0 syntax changes for hatch.
Change-Id: I36469cb3b0bcc595acf0e43808d6a574986cad68 Signed-off-by: Furquan Shaikh furquan@google.com --- M src/soc/intel/common/block/acpi/acpi/northbridge.asl 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/41519/3
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41519 )
Change subject: soc/intel/common/block/acpi: Fix error in shift operation for GPCL ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41519/1/src/soc/intel/common/block/... File src/soc/intel/common/block/acpi/acpi/northbridge.asl:
https://review.coreboot.org/c/coreboot/+/41519/1/src/soc/intel/common/block/... PS1, Line 232: <<
Done
Thanks again! Verified using --timeless option that the change effectively results in the same .rom file as without the ASL2.0 syntax.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41519 )
Change subject: soc/intel/common/block/acpi: Fix error in shift operation for GPCL ......................................................................
Patch Set 3: Code-Review+2
Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41519 )
Change subject: soc/intel/common/block/acpi: Fix error in shift operation for GPCL ......................................................................
soc/intel/common/block/acpi: Fix error in shift operation for GPCL
CB:41454 updated northbridge.asl to ASL2.0 syntax. During this, GPCL was incorrectly updated to use << (ShiftLeft) instead of >> (ShiftRight). This change fixes the error in GPCL by updating it to use >> (ShiftRight).
TEST=Verified using --timeless option to abuild that the resulting coreboot.rom is same as without the ASL2.0 syntax changes for hatch.
Change-Id: I36469cb3b0bcc595acf0e43808d6a574986cad68 Signed-off-by: Furquan Shaikh furquan@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/41519 Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/common/block/acpi/acpi/northbridge.asl 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl index 53b2188..bac0590 100644 --- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl +++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl @@ -229,7 +229,7 @@ /* Get PCIe Length */ Method (GPCL, 0, Serialized) { - Local0 = 0x10000000 << _SB.PCI0.MCHC.PXSZ + Local0 = 0x10000000 >> _SB.PCI0.MCHC.PXSZ Return (Local0) }
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41519 )
Change subject: soc/intel/common/block/acpi: Fix error in shift operation for GPCL ......................................................................
Patch Set 4:
Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/3590 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/3589 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/3588 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/3587
Please note: This test is under development and might not be accurate at all!
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41519 )
Change subject: soc/intel/common/block/acpi: Fix error in shift operation for GPCL ......................................................................
Patch Set 4: Code-Review+1