Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41519 )
Change subject: soc/intel/common/block/acpi: Fix error in shift operation for GPCL ......................................................................
soc/intel/common/block/acpi: Fix error in shift operation for GPCL
CB:41454 updated northbridge.asl to ASL2.0 syntax. During this, GPCL was incorrectly updated to use << (ShiftLeft) instead of >> (ShiftRight). This change fixes the error in GPCL by updating it to use >> (ShiftRight).
TEST=Verified using --timeless option to abuild that the resulting coreboot.rom is same as without the ASL2.0 syntax changes for hatch.
Change-Id: I36469cb3b0bcc595acf0e43808d6a574986cad68 Signed-off-by: Furquan Shaikh furquan@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/41519 Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/common/block/acpi/acpi/northbridge.asl 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl index 53b2188..bac0590 100644 --- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl +++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl @@ -229,7 +229,7 @@ /* Get PCIe Length */ Method (GPCL, 0, Serialized) { - Local0 = 0x10000000 << _SB.PCI0.MCHC.PXSZ + Local0 = 0x10000000 >> _SB.PCI0.MCHC.PXSZ Return (Local0) }