Change in ...coreboot[master]: sb/intel/common: Create a common PCH finalise implementation

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29977 )

Change subject: sb/intel/common: Create a common PCH finalise implementation
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Patch Set 2:

(4 comments)

https://review.coreboot.org/#/c/29977/2/src/southbridge/intel/common/finaliz... 
File src/southbridge/intel/common/finalize.c:

https://review.coreboot.org/#/c/29977/2/src/southbridge/intel/common/finaliz... 
PS2, Line 75: 	outb(POST_OS_BOOT, 0x80);
The name is just misleading. You might want to change that instead
(in another patch). It was particularly introduced for this purpose,
so it should stay.

https://review.coreboot.org/#/c/29977/2/src/southbridge/intel/common/finaliz... 
PS2, Line 61: pci_update_config32(lpc_dev, D31F0_ETR3, ~ETR3_CF9GR, ETR3_CF9LOCK);
> Public docs don't mention ETR3 for any platform before Sunrise Point, […]

It was just called differently: PMIR (same location).

https://review.coreboot.org/#/c/29977/2/src/southbridge/intel/common/finaliz... 
PS2, Line 62: 
            : 	/* PMSYNC */
            : 	RCBA32_OR(0x33c4, (1UL << 31));
> Public docs don't mention PMSYNC, as far as I can tell. So I'm not sure […]

It's HSW only. So `if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT))`?

https://review.coreboot.org/#/c/29977/2/src/southbridge/intel/common/pmutil.... 
File src/southbridge/intel/common/pmutil.h:

https://review.coreboot.org/#/c/29977/2/src/southbridge/intel/common/pmutil.... 
PS2, Line 25: D
F