4 comments:
File src/southbridge/intel/common/finalize.c:
Patch Set #2, Line 75: outb(POST_OS_BOOT, 0x80);
The name is just misleading. You might want to change that instead
(in another patch). It was particularly introduced for this purpose,
so it should stay.
Patch Set #2, Line 61: pci_update_config32(lpc_dev, D31F0_ETR3, ~ETR3_CF9GR, ETR3_CF9LOCK);
Public docs don't mention ETR3 for any platform before Sunrise Point, […]
It was just called differently: PMIR (same location).
/* PMSYNC */
RCBA32_OR(0x33c4, (1UL << 31));
Public docs don't mention PMSYNC, as far as I can tell. So I'm not sure […]
It's HSW only. So `if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT))`?
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