Change in coreboot[master]: mb/razer/blade_stealth_kbl/gpio: Convert configuration to macros
Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43411 )
Change subject: mb/razer/blade_stealth_kbl/gpio: Convert configuration to macros ......................................................................
mb/razer/blade_stealth_kbl/gpio: Convert configuration to macros
Use the intelp2m utility [1,2] to convert the current pad configuration format to the format with the the PAD_CFG() macros (*).
$ ./intelp2m -n -t 1 -p snr -file src/mainboard/51nb/x210/gpio.h
Unlike the raw DW0 and DW1 registers values from the inteltool dump, is more understandable and makes the code much cleaner.
[*] To do this, ignore some bit fields. See Patchset 1 |
Change-Id: Ie9da1246b784578c1e29acc5c61a918841de7468 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/razer/blade_stealth_kbl/gpio.h 1 file changed, 152 insertions(+), 152 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/43411/1
diff --git a/src/mainboard/razer/blade_stealth_kbl/gpio.h b/src/mainboard/razer/blade_stealth_kbl/gpio.h index c266dde..f8f5b08 100644 --- a/src/mainboard/razer/blade_stealth_kbl/gpio.h +++ b/src/mainboard/razer/blade_stealth_kbl/gpio.h @@ -10,158 +10,158 @@
/* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { - /* RCIN# */ _PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x0), - /* LAD0 */ _PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x3c00), - /* LAD1 */ _PAD_CFG_STRUCT(GPP_A2, 0x44000702, 0x3c00), - /* LAD2 */ _PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x3c00), - /* LAD3 */ _PAD_CFG_STRUCT(GPP_A4, 0x44000702, 0x3c00), - /* LFRAME# */ _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x0), - /* SERIRQ */ _PAD_CFG_STRUCT(GPP_A6, 0x44000702, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_A7, 0x84000102, 0x0), - /* CLKRUN# */ _PAD_CFG_STRUCT(GPP_A8, 0x44000702, 0x0), - /* CLKOUT_LPC0 */ _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1000), - /* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_A11, 0x40100102, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_A12, 0x04000201, 0x0), - /* SUSWARN# */ _PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x0), - /* SUS_STAT# */ _PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x0), - /* SUS_ACK# */ _PAD_CFG_STRUCT(GPP_A15, 0x44000700, 0x1000), - /* SD_1P8_SEL */ _PAD_CFG_STRUCT(GPP_A16, 0x44000700, 0x0), - /* SD_PWR_EN# */ _PAD_CFG_STRUCT(GPP_A17, 0x44000700, 0x0), - /* ISH_GP0 */ _PAD_CFG_STRUCT(GPP_A18, 0x44000702, 0x0), - /* ISH_GP1 */ _PAD_CFG_STRUCT(GPP_A19, 0x44000702, 0x0), - /* ISH_GP2 */ _PAD_CFG_STRUCT(GPP_A20, 0x44000702, 0x0), - /* ISH_GP3 */ _PAD_CFG_STRUCT(GPP_A21, 0x44000702, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_A22, 0x44000201, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_A23, 0x40100102, 0x0), - /* CORE_VID0 */ _PAD_CFG_STRUCT(GPP_B0, 0x44000700, 0x0), - /* CORE_VID1 */ _PAD_CFG_STRUCT(GPP_B1, 0x44000700, 0x0), - /* VRALERT# */ _PAD_CFG_STRUCT(GPP_B2, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B3, 0x80100100, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B4, 0x44000201, 0x0), - /* SRCCLKREQ0# */ _PAD_CFG_STRUCT(GPP_B5, 0x44000700, 0x0), - /* SRCCLKREQ1# */ _PAD_CFG_STRUCT(GPP_B6, 0x44000700, 0x0), - /* SRCCLKREQ2# */ _PAD_CFG_STRUCT(GPP_B7, 0x44000702, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B8, 0x44000300, 0x0), - /* SRCCLKREQ4# */ _PAD_CFG_STRUCT(GPP_B9, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B10, 0x44000300, 0x0), - /* EXT_PWR_GATE# */ _PAD_CFG_STRUCT(GPP_B11, 0x44000700, 0x0), - /* SLP_S0# */ _PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x0), - /* PLTRST# */ _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B14, 0x44000201, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B15, 0x44000200, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B16, 0x44000300, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B17, 0x42880100, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B18, 0x80880102, 0x3000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x0), - /* GSPI1_CLK */ _PAD_CFG_STRUCT(GPP_B20, 0x44000700, 0x1000), - /* GSPI1_MISO */ _PAD_CFG_STRUCT(GPP_B21, 0x44000700, 0x1000), - /* GSPI1_MOSI */ _PAD_CFG_STRUCT(GPP_B22, 0x44000700, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B23, 0x44000201, 0x1000), - /* SMBCLK */ _PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x0), - /* SMBDATA */ _PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x1000), - /* SML0CLK */ _PAD_CFG_STRUCT(GPP_C3, 0x44000702, 0x0), - /* SML0DATA */ _PAD_CFG_STRUCT(GPP_C4, 0x44000702, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_C5, 0x40900100, 0x1000), - /* RESERVED */ _PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00), - /* RESERVED */ _PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00), - /* UART0_RXD */ _PAD_CFG_STRUCT(GPP_C8, 0x44000702, 0x0), - /* UART0_TXD */ _PAD_CFG_STRUCT(GPP_C9, 0x44000700, 0x0), - /* UART0_RTS# */ _PAD_CFG_STRUCT(GPP_C10, 0x44000700, 0x0), - /* UART0_CTS# */ _PAD_CFG_STRUCT(GPP_C11, 0x44000700, 0x0), - /* UART1_RXD */ _PAD_CFG_STRUCT(GPP_C12, 0x44000702, 0x0), - /* UART1_TXD */ _PAD_CFG_STRUCT(GPP_C13, 0x44000700, 0x0), - /* UART1_RTS# */ _PAD_CFG_STRUCT(GPP_C14, 0x44000700, 0x0), - /* UART1_CTS# */ _PAD_CFG_STRUCT(GPP_C15, 0x44000702, 0x0), - /* I2C0_SDA */ _PAD_CFG_STRUCT(GPP_C16, 0x44000702, 0x0), - /* I2C0_SCL */ _PAD_CFG_STRUCT(GPP_C17, 0x44000702, 0x0), - /* I2C1_SDA */ _PAD_CFG_STRUCT(GPP_C18, 0x44000702, 0x0), - /* I2C1_SCL */ _PAD_CFG_STRUCT(GPP_C19, 0x44000702, 0x0), - /* UART2_RXD */ _PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x0), - /* UART2_TXD */ _PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0), - /* UART2_RTS# */ _PAD_CFG_STRUCT(GPP_C22, 0x44000700, 0x0), - /* UART2_CTS# */ _PAD_CFG_STRUCT(GPP_C23, 0x44000702, 0x0), - /* SPI1_CS# */ _PAD_CFG_STRUCT(GPP_D0, 0x44000700, 0x0), - /* SPI1_CLK */ _PAD_CFG_STRUCT(GPP_D1, 0x44000700, 0x0), - /* SPI1_MISO */ _PAD_CFG_STRUCT(GPP_D2, 0x44000700, 0x0), - /* SPI1_MOSI */ _PAD_CFG_STRUCT(GPP_D3, 0x44000700, 0x0), - /* FLASHTRIG */ _PAD_CFG_STRUCT(GPP_D4, 0x44000700, 0x0), - /* ISH_I2C0_SDA */ _PAD_CFG_STRUCT(GPP_D5, 0x44000700, 0x0), - /* ISH_I2C0_SCL */ _PAD_CFG_STRUCT(GPP_D6, 0x44000700, 0x0), - /* ISH_I2C1_SDA */ _PAD_CFG_STRUCT(GPP_D7, 0x44000700, 0x0), - /* ISH_I2C1_SCL */ _PAD_CFG_STRUCT(GPP_D8, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_D9, 0x40000100, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_D10, 0x40000100, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_D11, 0x40000100, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_D12, 0x40000100, 0x0), - /* ISH_UART0_RXD */ _PAD_CFG_STRUCT(GPP_D13, 0x44000700, 0x0), - /* ISH_UART0_TXD */ _PAD_CFG_STRUCT(GPP_D14, 0x44000700, 0x0), - /* ISH_UART0_RTS# */ _PAD_CFG_STRUCT(GPP_D15, 0x44000700, 0x0), - /* ISH_UART0_CTS# */ _PAD_CFG_STRUCT(GPP_D16, 0x44000700, 0x0), - /* DMIC_CLK1 */ _PAD_CFG_STRUCT(GPP_D17, 0x44000700, 0x0), - /* DMIC_DATA1 */ _PAD_CFG_STRUCT(GPP_D18, 0x44000700, 0x0), - /* DMIC_CLK0 */ _PAD_CFG_STRUCT(GPP_D19, 0x44000700, 0x0), - /* DMIC_DATA0 */ _PAD_CFG_STRUCT(GPP_D20, 0x44000700, 0x0), - /* SPI1_IO2 */ _PAD_CFG_STRUCT(GPP_D21, 0x44000700, 0x0), - /* SPI1_IO3 */ _PAD_CFG_STRUCT(GPP_D22, 0x44000700, 0x0), - /* I2S_MCLK */ _PAD_CFG_STRUCT(GPP_D23, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E0, 0x42880100, 0x0), - /* SATAXPCIE1 */ _PAD_CFG_STRUCT(GPP_E1, 0x44000700, 0x0), - /* SATAXPCIE2 */ _PAD_CFG_STRUCT(GPP_E2, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E3, 0x40000000, 0x0), - /* SATA_DEVSLP0 */ _PAD_CFG_STRUCT(GPP_E4, 0x04000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E5, 0x82880102, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E6, 0x44000200, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E7, 0x80180102, 0x0), - /* SATALED# */ _PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E9, 0x44000200, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E10, 0x44000201, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E11, 0x44000201, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E12, 0x44000300, 0x0), - /* DDPB_HPD0 */ _PAD_CFG_STRUCT(GPP_E13, 0x44000702, 0x0), - /* DDPC_HPD1 */ _PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E15, 0x42840102, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E16, 0x80880102, 0x0), - /* EDP_HPD */ _PAD_CFG_STRUCT(GPP_E17, 0x44000702, 0x0), - /* DDPB_CTRLCLK */ _PAD_CFG_STRUCT(GPP_E18, 0x44000700, 0x0), - /* DDPB_CTRLDATA */ _PAD_CFG_STRUCT(GPP_E19, 0x44000700, 0x1000), - /* DDPC_CTRLCLK */ _PAD_CFG_STRUCT(GPP_E20, 0x44000702, 0x0), - /* DDPC_CTRLDATA */ _PAD_CFG_STRUCT(GPP_E21, 0x44000702, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E22, 0x40900100, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E23, 0x84000200, 0x1000), - /* I2S2_SCLK */ _PAD_CFG_STRUCT(GPP_F0, 0x44000700, 0x0), - /* I2S2_SFRM */ _PAD_CFG_STRUCT(GPP_F1, 0x44000700, 0x0), - /* I2S2_TXD */ _PAD_CFG_STRUCT(GPP_F2, 0x44000700, 0x0), - /* I2S2_RXD */ _PAD_CFG_STRUCT(GPP_F3, 0x44000700, 0x0), - /* I2C2_SDA */ _PAD_CFG_STRUCT(GPP_F4, 0x44000700, 0x2000000), - /* I2C2_SCL */ _PAD_CFG_STRUCT(GPP_F5, 0x44000702, 0x2000000), - /* I2C3_SDA */ _PAD_CFG_STRUCT(GPP_F6, 0x44000702, 0x2000000), - /* I2C3_SCL */ _PAD_CFG_STRUCT(GPP_F7, 0x44000702, 0x2000000), - /* I2C4_SDA */ _PAD_CFG_STRUCT(GPP_F8, 0x44000702, 0x2000000), - /* I2C4_SCL */ _PAD_CFG_STRUCT(GPP_F9, 0x44000702, 0x2000000), - /* ISH_I2C2_SDA */ _PAD_CFG_STRUCT(GPP_F10, 0x44000b02, 0x2000000), - /* ISH_I2C2_SCL */ _PAD_CFG_STRUCT(GPP_F11, 0x44000b02, 0x2000000), - /* EMMC_CMD */ _PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_F13, 0x44000102, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_F14, 0x44000102, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_F15, 0x44000100, 0x0), - /* EMMC_DATA3 */ _PAD_CFG_STRUCT(GPP_F16, 0x44000700, 0x0), - /* EMMC_DATA4 */ _PAD_CFG_STRUCT(GPP_F17, 0x44000700, 0x0), - /* EMMC_DATA5 */ _PAD_CFG_STRUCT(GPP_F18, 0x44000700, 0x0), - /* EMMC_DATA6 */ _PAD_CFG_STRUCT(GPP_F19, 0x44000700, 0x0), - /* EMMC_DATA7 */ _PAD_CFG_STRUCT(GPP_F20, 0x44000700, 0x0), - /* EMMC_RCLK */ _PAD_CFG_STRUCT(GPP_F21, 0x44000700, 0x0), - /* EMMC_CLK */ _PAD_CFG_STRUCT(GPP_F22, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_F23, 0x40100100, 0x0), - /* SD_CMD */ _PAD_CFG_STRUCT(GPP_G0, 0x44000700, 0x0), - /* SD_DATA0 */ _PAD_CFG_STRUCT(GPP_G1, 0x44000700, 0x0), - /* SD_DATA1 */ _PAD_CFG_STRUCT(GPP_G2, 0x44000700, 0x0), - /* SD_DATA2 */ _PAD_CFG_STRUCT(GPP_G3, 0x44000700, 0x0), - /* SD_DATA3 */ _PAD_CFG_STRUCT(GPP_G4, 0x44000700, 0x0), - /* SD_CD# */ _PAD_CFG_STRUCT(GPP_G5, 0x44000700, 0x0), - /* SD_CLK */ _PAD_CFG_STRUCT(GPP_G6, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_G7, 0x44000100, 0x0), +/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* LAD0 */ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* LAD1 */ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* LAD2 */ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* LAD3 */ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_A7, NONE, PLTRST, OFF, ACPI), +/* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* CLKOUT_LPC1 */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_APIC(GPP_A11, NONE, DEEP), +/* GPIO */ PAD_CFG_GPO(GPP_A12, 1, PWROK), +/* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SUS_ACK# */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_GP0 */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_GP1 */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_GP2 */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_GP3 */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPO(GPP_A22, 1, DEEP), +/* GPIO */ PAD_CFG_GPI_APIC(GPP_A23, NONE, DEEP), +/* CORE_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* CORE_VID1 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* VRALERT# */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), +/* GPIO */ PAD_CFG_GPO(GPP_B4, 1, DEEP), +/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_NC(GPP_B8, NONE), +/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_NC(GPP_B10, NONE), +/* EXT_PWR_GATE# */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_TERM_GPO(GPP_B14, 1, 20K_PD, DEEP), +/* GPIO */ PAD_CFG_GPO(GPP_B15, 0, DEEP), +/* GPIO */ PAD_NC(GPP_B16, NONE), +/* GPIO */ PAD_CFG_GPI_ACPI_SCI(GPP_B17, 20K_PD, DEEP, INVERT), +/* GPIO */ PAD_CFG_GPI_SCI(GPP_B18, 20K_PU, PLTRST, LEVEL, INVERT), +/* GPIO */ PAD_NC(GPP_B19, NONE), +/* GSPI1_CLK */ PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GSPI1_MISO */ PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_TERM_GPO(GPP_B23, 1, 20K_PD, DEEP), +/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SMBDATA */ PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_TERM_GPO(GPP_C2, 1, 20K_PD, DEEP), +/* SML0CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_APIC_INVERT(GPP_C5, 20K_PD, DEEP), +/* RESERVED - GPP_C6 */ +/* RESERVED - GPP_C7 */ +/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART0_RTS# */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART0_CTS# */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART1_RXD */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART1_TXD */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART1_RTS# */ PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART1_CTS# */ PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART2_RTS# */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART2_CTS# */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SPI1_CS# */ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SPI1_CLK */ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SPI1_MISO */ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SPI1_MOSI */ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* FLASHTRIG */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_I2C0_SDA */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_I2C0_SCL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D9, NONE, DEEP, LEVEL, ACPI), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D10, NONE, DEEP, LEVEL, ACPI), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D11, NONE, DEEP, LEVEL, ACPI), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D12, NONE, DEEP, LEVEL, ACPI), +/* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_UART0_RTS# */ PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_UART0_CTS# */ PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SPI1_IO2 */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SPI1_IO3 */ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_ACPI_SCI(GPP_E0, NONE, DEEP, INVERT), +/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPIO_BIDIRECT(GPP_E3, 0, NONE, DEEP, LEVEL, ACPI), +/* SATA_DEVSLP0 */ PAD_CFG_NF(GPP_E4, NONE, PWROK, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_ACPI_SCI(GPP_E5, NONE, PLTRST, INVERT), +/* GPIO */ PAD_CFG_GPO(GPP_E6, 0, DEEP), +/* GPIO */ PAD_CFG_GPI_DUAL_ROUTE(GPP_E7, NONE, PLTRST, LEVEL, IOAPIC, SCI), +/* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPO(GPP_E9, 0, DEEP), +/* GPIO */ PAD_CFG_TERM_GPO(GPP_E10, 1, 20K_PD, DEEP), +/* GPIO */ PAD_CFG_TERM_GPO(GPP_E11, 1, 20K_PD, DEEP), +/* GPIO */ PAD_NC(GPP_E12, NONE), +/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, INVERT), +/* GPIO */ PAD_CFG_GPI_SCI(GPP_E16, NONE, PLTRST, LEVEL, INVERT), +/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_APIC_INVERT(GPP_E22, NONE, DEEP), +/* GPIO */ PAD_CFG_TERM_GPO(GPP_E23, 0, 20K_PD, PLTRST), +/* I2S2_SCLK */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2S2_SFRM */ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2S2_TXD */ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2S2_RXD */ PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C3_SDA */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C3_SCL */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C4_SCL */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_I2C2_SDA */ PAD_CFG_NF(GPP_F10, NONE, DEEP, NF2), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_I2C2_SCL */ PAD_CFG_NF(GPP_F11, NONE, DEEP, NF2), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, DEEP, OFF, ACPI), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, ACPI), +/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_APIC(GPP_F23, NONE, DEEP), +/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_G7, NONE, DEEP, OFF, ACPI), };
#endif
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43411 )
Change subject: mb/razer/blade_stealth_kbl/gpio: Convert configuration to macros ......................................................................
Patch Set 1:
(110 comments)
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... File src/mainboard/razer/blade_stealth_kbl/gpio.h:
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 13: /* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 14: /* LAD0 */ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 15: /* LAD1 */ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 16: /* LAD2 */ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 17: /* LAD3 */ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 18: /* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 19: /* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 21: /* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 22: /* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 23: /* CLKOUT_LPC1 */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 26: /* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 27: /* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 28: /* SUS_ACK# */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 29: /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 30: /* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 31: /* ISH_GP0 */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 32: /* ISH_GP1 */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 33: /* ISH_GP2 */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 34: /* ISH_GP3 */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 37: /* CORE_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 38: /* CORE_VID1 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 39: /* VRALERT# */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 42: /* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 43: /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 44: /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 46: /* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 48: /* EXT_PWR_GATE# */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 49: /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 50: /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 57: /* GSPI1_CLK */ PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 58: /* GSPI1_MISO */ PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 59: /* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 61: /* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 62: /* SMBDATA */ PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 64: /* SML0CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 65: /* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 69: /* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 70: /* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 71: /* UART0_RTS# */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 72: /* UART0_CTS# */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 73: /* UART1_RXD */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 74: /* UART1_TXD */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 75: /* UART1_RTS# */ PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 76: /* UART1_CTS# */ PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 77: /* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 78: /* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 79: /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 80: /* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 81: /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 82: /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 83: /* UART2_RTS# */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 84: /* UART2_CTS# */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 85: /* SPI1_CS# */ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 86: /* SPI1_CLK */ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 87: /* SPI1_MISO */ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 88: /* SPI1_MOSI */ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 89: /* FLASHTRIG */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 90: /* ISH_I2C0_SDA */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 91: /* ISH_I2C0_SCL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 92: /* ISH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 93: /* ISH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 98: /* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 99: /* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 100: /* ISH_UART0_RTS# */ PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 101: /* ISH_UART0_CTS# */ PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 102: /* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 103: /* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 104: /* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 105: /* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 106: /* SPI1_IO2 */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 107: /* SPI1_IO3 */ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 108: /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 110: /* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 111: /* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 113: /* SATA_DEVSLP0 */ PAD_CFG_NF(GPP_E4, NONE, PWROK, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 117: /* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 122: /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 123: /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 126: /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 127: /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 128: /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 129: /* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 130: /* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 133: /* I2S2_SCLK */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 134: /* I2S2_SFRM */ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 135: /* I2S2_TXD */ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 136: /* I2S2_RXD */ PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 137: /* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 138: /* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 139: /* I2C3_SDA */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 140: /* I2C3_SCL */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 141: /* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 142: /* I2C4_SCL */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 143: /* ISH_I2C2_SDA */ PAD_CFG_NF(GPP_F10, NONE, DEEP, NF2), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 144: /* ISH_I2C2_SCL */ PAD_CFG_NF(GPP_F11, NONE, DEEP, NF2), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 145: /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 149: /* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 150: /* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 151: /* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 152: /* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 153: /* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 154: /* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 155: /* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 157: /* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 158: /* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 159: /* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 160: /* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 161: /* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 162: /* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/43411/1/src/mainboard/razer/blade_s... PS1, Line 163: /* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ line over 96 characters
Maxim Polyakov has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/43411 )
Change subject: mb/razer/blade_stealth_kbl/gpio: Convert configuration to macros ......................................................................
mb/razer/blade_stealth_kbl/gpio: Convert configuration to macros
Use the intelp2m utility [1,2] to convert the current pad configuration format to the format with the the PAD_CFG() macros (*).
$ ./intelp2m -n -t 1 -p snr -file src/mainboard/51nb/x210/gpio.h
Unlike the raw DW0 and DW1 registers values from the inteltool dump, is more understandable and makes the code much cleaner.
[*] To do this, ignore some bit fields. See Patchset 1 | d9125e4cb0: https://review.coreboot.org/c/coreboot/+/43411/1
Change-Id: Ie9da1246b784578c1e29acc5c61a918841de7468 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/razer/blade_stealth_kbl/gpio.h 1 file changed, 152 insertions(+), 153 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/43411/2
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43411
to look at the new patch set (#3).
Change subject: mb/razer/blade_stealth_kbl/gpio: Convert configuration to macros ......................................................................
mb/razer/blade_stealth_kbl/gpio: Convert configuration to macros
Use the intelp2m utility [1,2] to convert the current pad configuration format to the format with the the PAD_CFG() macros (*).
$ ./intelp2m -n -t 1 -p snr -file src/mainboard/51nb/x210/gpio.h
Unlike the raw DW0 and DW1 registers values from the inteltool dump, is more understandable and makes the code much cleaner.
[*] To do this, ignore some bit fields. See Patchset 1 | d9125e4cb0: https://review.coreboot.org/c/coreboot/+/43411/1
Change-Id: Ie9da1246b784578c1e29acc5c61a918841de7468 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/razer/blade_stealth_kbl/gpio.h 1 file changed, 152 insertions(+), 153 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/43411/3
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43411
to look at the new patch set (#4).
Change subject: mb/razer/blade_stealth_kbl/gpio: Convert configuration to macros ......................................................................
mb/razer/blade_stealth_kbl/gpio: Convert configuration to macros
Use the intelp2m utility [1,2] to convert the current pad configuration format to the format with the the PAD_CFG() macros (*).
$ ./intelp2m -n -t 1 -p snr -file src/mainboard/51nb/x210/gpio.h
Unlike the raw DW0 and DW1 registers values from the inteltool dump, is more understandable and makes the code much cleaner.
[*] To do this, ignore some bit fields. See Patchset 1 | d9125e4cb0: https://review.coreboot.org/c/coreboot/+/43411/1
Change-Id: Ie9da1246b784578c1e29acc5c61a918841de7468 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/razer/blade_stealth_kbl/gpio.h 1 file changed, 152 insertions(+), 153 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/43411/4
Hello build bot (Jenkins), Benjamin Doron, Jonathan Neuschäfer, Paul Menzel, Mimoja, Angel Pons, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43411
to look at the new patch set (#6).
Change subject: mb/razer/blade_stealth_kbl/gpio: Convert configuration to macros ......................................................................
mb/razer/blade_stealth_kbl/gpio: Convert configuration to macros
Use the intelp2m utility [1,2] to convert the current pad configuration format to the format with the the PAD_CFG() macros (*).
$ ./intelp2m -n -t 1 -p snr -file src/mainboard/51nb/x210/gpio.h
Unlike the raw DW0 and DW1 registers values from the inteltool dump, is more understandable and makes the code much cleaner.
[*] To do this, ignore some bit fields. See Patchset 1 | d9125e4cb0: https://review.coreboot.org/c/coreboot/+/43411/1
[1] https://github.com/maxpoliak/pch-pads-parser [2] https://review.coreboot.org/c/coreboot/+/35643
Change-Id: Ie9da1246b784578c1e29acc5c61a918841de7468 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/razer/blade_stealth_kbl/gpio.h 1 file changed, 152 insertions(+), 153 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/43411/6
Mimoja has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43411 )
Change subject: mb/razer/blade_stealth_kbl/gpio: Convert configuration to macros ......................................................................
Patch Set 6:
I sadly cannot boot-test right now, but looks good to me. It lines up with my initial notes on those pads that are not NFs
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43411 )
Change subject: mb/razer/blade_stealth_kbl: 3/3 Convert field macros to PAD_CFG ......................................................................
Patch Set 11:
This change is ready for review.
Hello build bot (Jenkins), Benjamin Doron, Jonathan Neuschäfer, Paul Menzel, Mimoja, Angel Pons, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43411
to look at the new patch set (#13).
Change subject: mb/razer/blade_stealth_kbl: 3/3 Convert field macros to PAD_CFG ......................................................................
mb/razer/blade_stealth_kbl: 3/3 Convert field macros to PAD_CFG
Converts bit field macros to target PAD_CFG_*() macros. To do this, the following command was used:
./intelp2m -n -t 1 -file ../../src/mainboard/razer/blade_stealth_kbl/ gpio.h
This is part of the patch set "mb/razer/blade_stealth_kbl/gpio: Rewrite pad config using intelp2m":
CB:43857 - 1/3 Decode raw register values CB:43858 - 2/3 Exclude fields for PAD_CFG CB:43411 - 3/3 Convert field macros to PAD_CFG
Tested with BUILD_TIMELESS=1, Razer Blade Stealth, remains identical.
Change-Id: Ie9da1246b784578c1e29acc5c61a918841de7468 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/razer/blade_stealth_kbl/gpio.h 1 file changed, 164 insertions(+), 152 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/43411/13
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43411 )
Change subject: mb/razer/blade_stealth_kbl: 3/3 Convert field macros to PAD_CFG ......................................................................
Patch Set 14: Code-Review+2
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43411 )
Change subject: mb/razer/blade_stealth_kbl: 3/3 Convert field macros to PAD_CFG ......................................................................
Patch Set 14:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43411/14/src/mainboard/razer/blade_... File src/mainboard/razer/blade_stealth_kbl/gpio.h:
https://review.coreboot.org/c/coreboot/+/43411/14/src/mainboard/razer/blade_... PS14, Line 9: /* : * Bidirectional GPIO port when both RX and TX buffer is enabled : * TODO: move this macros to src/soc/intel/common/block/include/intelblocks/gpio_defs.h : */ : #ifndef PAD_CFG_GPIO_BIDIRECT : #define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \ : _PAD_CFG_STRUCT(pad, \ : PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ : PAD_BUF(NO_DISABLE) | val, \ : PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) : #endif todo
Hello build bot (Jenkins), Benjamin Doron, Jonathan Neuschäfer, Paul Menzel, Mimoja, Angel Pons, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43411
to look at the new patch set (#15).
Change subject: mb/razer/blade_stealth_kbl: 3/3 Convert field macros to PAD_CFG ......................................................................
mb/razer/blade_stealth_kbl: 3/3 Convert field macros to PAD_CFG
Converts bit field macros to target PAD_CFG_*() macros. To do this, the following command was used:
./intelp2m -n -t 1 -file ../../src/mainboard/razer/blade_stealth_kbl/ gpio.h
This is part of the patch set "mb/razer/blade_stealth_kbl/gpio: Rewrite pad config using intelp2m":
CB:43857 - 1/3 Decode raw register values CB:43858 - 2/3 Exclude fields for PAD_CFG CB:43411 - 3/3 Convert field macros to PAD_CFG
Tested with BUILD_TIMELESS=1, Razer Blade Stealth, remains identical.
Change-Id: Ie9da1246b784578c1e29acc5c61a918841de7468 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/razer/blade_stealth_kbl/gpio.h 1 file changed, 164 insertions(+), 152 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/43411/15
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43411 )
Change subject: mb/razer/blade_stealth_kbl: 3/3 Convert field macros to PAD_CFG ......................................................................
Patch Set 15:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43411/14/src/mainboard/razer/blade_... File src/mainboard/razer/blade_stealth_kbl/gpio.h:
https://review.coreboot.org/c/coreboot/+/43411/14/src/mainboard/razer/blade_... PS14, Line 9: /* : * Bidirectional GPIO port when both RX and TX buffer is enabled : * TODO: move this macros to src/soc/intel/common/block/include/intelblocks/gpio_defs.h : */ : #ifndef PAD_CFG_GPIO_BIDIRECT : #define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \ : _PAD_CFG_STRUCT(pad, \ : PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ : PAD_BUF(NO_DISABLE) | val, \ : PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) : #endif
todo
Done
Hello build bot (Jenkins), Benjamin Doron, Jonathan Neuschäfer, Paul Menzel, Mimoja, Angel Pons, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43411
to look at the new patch set (#17).
Change subject: mb/razer/blade_stealth_kbl: 3/3 Convert field macros to PAD_CFG ......................................................................
mb/razer/blade_stealth_kbl: 3/3 Convert field macros to PAD_CFG
Converts bit field macros to target PAD_CFG_*() macros. To do this, the following command was used:
./intelp2m -n -t 1 -file ../../src/mainboard/razer/blade_stealth_kbl/ gpio.h
This is part of the patch set "mb/razer/blade_stealth_kbl/gpio: Rewrite pad config using intelp2m":
CB:43857 - 1/3 Decode raw register values CB:43858 - 2/3 Exclude fields for PAD_CFG CB:43411 - 3/3 Convert field macros to PAD_CFG
Tested with BUILD_TIMELESS=1, Razer Blade Stealth, remains identical.
Change-Id: Ie9da1246b784578c1e29acc5c61a918841de7468 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/razer/blade_stealth_kbl/gpio.h 1 file changed, 164 insertions(+), 152 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/43411/17
Hello build bot (Jenkins), Benjamin Doron, Jonathan Neuschäfer, Paul Menzel, Mimoja, Angel Pons, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43411
to look at the new patch set (#18).
Change subject: mb/razer/blade_stealth_kbl: 3/3 Convert field macros to PAD_CFG ......................................................................
mb/razer/blade_stealth_kbl: 3/3 Convert field macros to PAD_CFG
Converts bit field macros to target PAD_CFG_*() macros. To do this, the following command was used:
./intelp2m -n -t 1 -file ../../src/mainboard/razer/blade_stealth_kbl/ gpio.h
This is part of the patch set "mb/razer/blade_stealth_kbl/gpio: Rewrite pad config using intelp2m":
CB:43857 - 1/3 Decode raw register values CB:43858 - 2/3 Exclude fields for PAD_CFG CB:43411 - 3/3 Convert field macros to PAD_CFG
Tested with BUILD_TIMELESS=1, Razer Blade Stealth, remains identical.
Change-Id: Ie9da1246b784578c1e29acc5c61a918841de7468 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/razer/blade_stealth_kbl/gpio.h 1 file changed, 164 insertions(+), 152 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/43411/18
Hello build bot (Jenkins), Benjamin Doron, Jonathan Neuschäfer, Paul Menzel, Mimoja, Angel Pons, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43411
to look at the new patch set (#19).
Change subject: mb/razer/blade_stealth_kbl: 3/3 Convert field macros to PAD_CFG ......................................................................
mb/razer/blade_stealth_kbl: 3/3 Convert field macros to PAD_CFG
Converts bit field macros to target PAD_CFG_*() macros. To do this, the following command was used:
./intelp2m -n -t 1 -file ../../src/mainboard/razer/blade_stealth_kbl/ gpio.h
This is part of the patch set "mb/razer/blade_stealth_kbl/gpio: Rewrite pad config using intelp2m":
CB:43857 - 1/3 Decode raw register values CB:43858 - 2/3 Exclude fields for PAD_CFG CB:43411 - 3/3 Convert field macros to PAD_CFG
Tested with BUILD_TIMELESS=1, Razer Blade Stealth, remains identical.
Change-Id: Ie9da1246b784578c1e29acc5c61a918841de7468 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/razer/blade_stealth_kbl/gpio.h 1 file changed, 164 insertions(+), 152 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/43411/19
Hello build bot (Jenkins), Benjamin Doron, Jonathan Neuschäfer, Paul Menzel, Mimoja, Angel Pons, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43411
to look at the new patch set (#20).
Change subject: mb/razer/blade_stealth_kbl: 3/3 Convert field macros to PAD_CFG ......................................................................
mb/razer/blade_stealth_kbl: 3/3 Convert field macros to PAD_CFG
Converts bit field macros to target PAD_CFG_*() macros. To do this, the following command was used:
./intelp2m -n -t 1 -file ../../src/mainboard/razer/blade_stealth_kbl/ gpio.h
This is part of the patch set "mb/razer/blade_stealth_kbl/gpio: Rewrite pad config using intelp2m":
CB:43857 - 1/3 Decode raw register values CB:43858 - 2/3 Exclude fields for PAD_CFG CB:43411 - 3/3 Convert field macros to PAD_CFG
Tested with BUILD_TIMELESS=1, Razer Blade Stealth, remains identical.
Change-Id: Ie9da1246b784578c1e29acc5c61a918841de7468 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/razer/blade_stealth_kbl/gpio.h 1 file changed, 164 insertions(+), 152 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/43411/20
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43411 )
Change subject: mb/razer/blade_stealth_kbl: 3/3 Convert field macros to PAD_CFG ......................................................................
Patch Set 20:
Any comments? Maybe +2?
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43411 )
Change subject: mb/razer/blade_stealth_kbl: 3/3 Convert field macros to PAD_CFG ......................................................................
Patch Set 20: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/43411/20/src/mainboard/razer/blade_... File src/mainboard/razer/blade_stealth_kbl/gpio.h:
https://review.coreboot.org/c/coreboot/+/43411/20/src/mainboard/razer/blade_... PS20, Line 11: todo oh, sorry. I didn't mean "write it lc" but just marked that section as TODO until the bidir macro gets in
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43411 )
Change subject: mb/razer/blade_stealth_kbl: 3/3 Convert field macros to PAD_CFG ......................................................................
Patch Set 20:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43411/20/src/mainboard/razer/blade_... File src/mainboard/razer/blade_stealth_kbl/gpio.h:
https://review.coreboot.org/c/coreboot/+/43411/20/src/mainboard/razer/blade_... PS20, Line 11: todo
oh, sorry. […]
In that case, can I mark it as ack?
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43411 )
Change subject: mb/razer/blade_stealth_kbl: 3/3 Convert field macros to PAD_CFG ......................................................................
Patch Set 21:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43411/20/src/mainboard/razer/blade_... File src/mainboard/razer/blade_stealth_kbl/gpio.h:
https://review.coreboot.org/c/coreboot/+/43411/20/src/mainboard/razer/blade_... PS20, Line 11: todo
In that case, can I mark it as ack?
Ack
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43411 )
Change subject: mb/razer/blade_stealth_kbl: 3/3 Convert field macros to PAD_CFG ......................................................................
mb/razer/blade_stealth_kbl: 3/3 Convert field macros to PAD_CFG
Converts bit field macros to target PAD_CFG_*() macros. To do this, the following command was used:
./intelp2m -n -t 1 -file ../../src/mainboard/razer/blade_stealth_kbl/ gpio.h
This is part of the patch set "mb/razer/blade_stealth_kbl/gpio: Rewrite pad config using intelp2m":
CB:43857 - 1/3 Decode raw register values CB:43858 - 2/3 Exclude fields for PAD_CFG CB:43411 - 3/3 Convert field macros to PAD_CFG
Tested with BUILD_TIMELESS=1, Razer Blade Stealth, remains identical.
Change-Id: Ie9da1246b784578c1e29acc5c61a918841de7468 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/43411 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Michael Niewöhner foss@mniewoehner.de --- M src/mainboard/razer/blade_stealth_kbl/gpio.h 1 file changed, 164 insertions(+), 152 deletions(-)
Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved
diff --git a/src/mainboard/razer/blade_stealth_kbl/gpio.h b/src/mainboard/razer/blade_stealth_kbl/gpio.h index 6b29a2c..2b7df01 100644 --- a/src/mainboard/razer/blade_stealth_kbl/gpio.h +++ b/src/mainboard/razer/blade_stealth_kbl/gpio.h @@ -6,164 +6,176 @@ #include <soc/gpe.h> #include <soc/gpio.h>
+/* + * Bidirectional GPIO port when both RX and TX buffer is enabled + * todo: move this macros to src/soc/intel/common/block/include/intelblocks/gpio_defs.h + */ +#ifndef PAD_CFG_GPIO_BIDIRECT +#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ + PAD_BUF(NO_DISABLE) | val, \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) +#endif + #ifndef __ACPI__
/* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { -/* RCIN# */ _PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* LAD0 */ _PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(NATIVE)), -/* LAD1 */ _PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(NATIVE)), -/* LAD2 */ _PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(NATIVE)), -/* LAD3 */ _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(NATIVE)), -/* LFRAME# */ _PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SERIRQ */ _PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), -/* CLKRUN# */ _PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* CLKOUT_LPC0 */ _PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(DN_20K)), -/* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(DN_20K)), -/* GPIO */ _PAD_CFG_STRUCT(GPP_A11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_A12, PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), -/* SUSWARN# */ _PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SUS_STAT# */ _PAD_CFG_STRUCT(GPP_A14, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SUS_ACK# */ _PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(DN_20K)), -/* SD_1P8_SEL */ _PAD_CFG_STRUCT(GPP_A16, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SD_PWR_EN# */ _PAD_CFG_STRUCT(GPP_A17, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* ISH_GP0 */ _PAD_CFG_STRUCT(GPP_A18, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* ISH_GP1 */ _PAD_CFG_STRUCT(GPP_A19, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* ISH_GP2 */ _PAD_CFG_STRUCT(GPP_A20, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* ISH_GP3 */ _PAD_CFG_STRUCT(GPP_A21, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_A22, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_A23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), 0), -/* CORE_VID0 */ _PAD_CFG_STRUCT(GPP_B0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* CORE_VID1 */ _PAD_CFG_STRUCT(GPP_B1, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* VRALERT# */ _PAD_CFG_STRUCT(GPP_B2, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B3, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), -/* SRCCLKREQ0# */ _PAD_CFG_STRUCT(GPP_B5, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SRCCLKREQ1# */ _PAD_CFG_STRUCT(GPP_B6, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SRCCLKREQ2# */ _PAD_CFG_STRUCT(GPP_B7, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B8, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* SRCCLKREQ4# */ _PAD_CFG_STRUCT(GPP_B9, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B10, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* EXT_PWR_GATE# */ _PAD_CFG_STRUCT(GPP_B11, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SLP_S0# */ _PAD_CFG_STRUCT(GPP_B12, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* PLTRST# */ _PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(DN_20K)), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B15, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B16, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B17, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), PAD_PULL(DN_20K)), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B18, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), PAD_PULL(UP_20K)), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B19, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* GSPI1_CLK */ _PAD_CFG_STRUCT(GPP_B20, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(DN_20K)), -/* GSPI1_MISO */ _PAD_CFG_STRUCT(GPP_B21, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(DN_20K)), -/* GSPI1_MOSI */ _PAD_CFG_STRUCT(GPP_B22, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(DN_20K)), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(DN_20K)), -/* SMBCLK */ _PAD_CFG_STRUCT(GPP_C0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SMBDATA */ _PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(DN_20K)), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(DN_20K)), -/* SML0CLK */ _PAD_CFG_STRUCT(GPP_C3, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SML0DATA */ _PAD_CFG_STRUCT(GPP_C4, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(IOAPIC) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), PAD_PULL(DN_20K)), +/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), +/* LAD0 */ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), +/* LAD1 */ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), +/* LAD2 */ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), +/* LAD3 */ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), +/* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), +/* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_A7, NONE, PLTRST, OFF, ACPI), +/* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), +/* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), +/* CLKOUT_LPC1 */ PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), +/* GPIO */ PAD_CFG_GPI_APIC_HIGH(GPP_A11, NONE, DEEP), +/* GPIO */ PAD_CFG_GPO(GPP_A12, 1, PWROK), +/* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), +/* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), +/* SUS_ACK# */ PAD_CFG_NF(GPP_A15, DN_20K, DEEP, NF1), +/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), +/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), +/* ISH_GP0 */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), +/* ISH_GP1 */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), +/* ISH_GP2 */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), +/* ISH_GP3 */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), +/* GPIO */ PAD_CFG_GPO(GPP_A22, 1, DEEP), +/* GPIO */ PAD_CFG_GPI_APIC_HIGH(GPP_A23, NONE, DEEP), +/* CORE_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), +/* CORE_VID1 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), +/* VRALERT# */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), +/* GPIO */ PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), +/* GPIO */ PAD_CFG_GPO(GPP_B4, 1, DEEP), +/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), +/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), +/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), +/* GPIO */ PAD_NC(GPP_B8, NONE), +/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), +/* GPIO */ PAD_NC(GPP_B10, NONE), +/* EXT_PWR_GATE# */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), +/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), +/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), +/* GPIO */ PAD_CFG_TERM_GPO(GPP_B14, 1, DN_20K, DEEP), +/* GPIO */ PAD_CFG_GPO(GPP_B15, 0, DEEP), +/* GPIO */ PAD_NC(GPP_B16, NONE), +/* GPIO */ PAD_CFG_GPI_SCI(GPP_B17, DN_20K, DEEP, EDGE_SINGLE, INVERT), +/* GPIO */ PAD_CFG_GPI_SCI(GPP_B18, UP_20K, PLTRST, LEVEL, INVERT), +/* GPIO */ PAD_NC(GPP_B19, NONE), +/* GSPI1_CLK */ PAD_CFG_NF(GPP_B20, DN_20K, DEEP, NF1), +/* GSPI1_MISO */ PAD_CFG_NF(GPP_B21, DN_20K, DEEP, NF1), +/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, DN_20K, DEEP, NF1), +/* GPIO */ PAD_CFG_TERM_GPO(GPP_B23, 1, DN_20K, DEEP), +/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), +/* SMBDATA */ PAD_CFG_NF(GPP_C1, DN_20K, DEEP, NF1), +/* GPIO */ PAD_CFG_TERM_GPO(GPP_C2, 1, DN_20K, DEEP), +/* SML0CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), +/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), +/* GPIO */ PAD_CFG_GPI_APIC_LOW(GPP_C5, DN_20K, DEEP), /* GPP_C6 - RESERVED */ /* GPP_C7 - RESERVED */ -/* UART0_RXD */ _PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* UART0_TXD */ _PAD_CFG_STRUCT(GPP_C9, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* UART0_RTS# */ _PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* UART0_CTS# */ _PAD_CFG_STRUCT(GPP_C11, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* UART1_RXD */ _PAD_CFG_STRUCT(GPP_C12, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* UART1_TXD */ _PAD_CFG_STRUCT(GPP_C13, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* UART1_RTS# */ _PAD_CFG_STRUCT(GPP_C14, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* UART1_CTS# */ _PAD_CFG_STRUCT(GPP_C15, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* I2C0_SDA */ _PAD_CFG_STRUCT(GPP_C16, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* I2C0_SCL */ _PAD_CFG_STRUCT(GPP_C17, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* I2C1_SDA */ _PAD_CFG_STRUCT(GPP_C18, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* I2C1_SCL */ _PAD_CFG_STRUCT(GPP_C19, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* UART2_RXD */ _PAD_CFG_STRUCT(GPP_C20, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* UART2_TXD */ _PAD_CFG_STRUCT(GPP_C21, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* UART2_RTS# */ _PAD_CFG_STRUCT(GPP_C22, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* UART2_CTS# */ _PAD_CFG_STRUCT(GPP_C23, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SPI1_CS# */ _PAD_CFG_STRUCT(GPP_D0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SPI1_CLK */ _PAD_CFG_STRUCT(GPP_D1, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SPI1_MISO */ _PAD_CFG_STRUCT(GPP_D2, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SPI1_MOSI */ _PAD_CFG_STRUCT(GPP_D3, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* FLASHTRIG */ _PAD_CFG_STRUCT(GPP_D4, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* ISH_I2C0_SDA */ _PAD_CFG_STRUCT(GPP_D5, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* ISH_I2C0_SCL */ _PAD_CFG_STRUCT(GPP_D6, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* ISH_I2C1_SDA */ _PAD_CFG_STRUCT(GPP_D7, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* ISH_I2C1_SCL */ _PAD_CFG_STRUCT(GPP_D8, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D9, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(TX_DISABLE), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D10, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(TX_DISABLE), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(TX_DISABLE), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(TX_DISABLE), 0), -/* ISH_UART0_RXD */ _PAD_CFG_STRUCT(GPP_D13, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* ISH_UART0_TXD */ _PAD_CFG_STRUCT(GPP_D14, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* ISH_UART0_RTS# */ _PAD_CFG_STRUCT(GPP_D15, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* ISH_UART0_CTS# */ _PAD_CFG_STRUCT(GPP_D16, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* DMIC_CLK1 */ _PAD_CFG_STRUCT(GPP_D17, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* DMIC_DATA1 */ _PAD_CFG_STRUCT(GPP_D18, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* DMIC_CLK0 */ _PAD_CFG_STRUCT(GPP_D19, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* DMIC_DATA0 */ _PAD_CFG_STRUCT(GPP_D20, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SPI1_IO2 */ _PAD_CFG_STRUCT(GPP_D21, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SPI1_IO3 */ _PAD_CFG_STRUCT(GPP_D22, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* I2S_MCLK */ _PAD_CFG_STRUCT(GPP_D23, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E0, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), 0), -/* SATAXPCIE1 */ _PAD_CFG_STRUCT(GPP_E1, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SATAXPCIE2 */ _PAD_CFG_STRUCT(GPP_E2, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E3, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), -/* SATA_DEVSLP0 */ _PAD_CFG_STRUCT(GPP_E4, PAD_FUNC(NF1), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E5, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E6, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E7, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_BUF(TX_DISABLE), 0), -/* SATALED# */ _PAD_CFG_STRUCT(GPP_E8, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E10, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(DN_20K)), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(DN_20K)), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* DDPB_HPD0 */ _PAD_CFG_STRUCT(GPP_E13, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* DDPC_HPD1 */ _PAD_CFG_STRUCT(GPP_E14, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E15, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E16, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), 0), -/* EDP_HPD */ _PAD_CFG_STRUCT(GPP_E17, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* DDPB_CTRLCLK */ _PAD_CFG_STRUCT(GPP_E18, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* DDPB_CTRLDATA */ _PAD_CFG_STRUCT(GPP_E19, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(DN_20K)), -/* DDPC_CTRLCLK */ _PAD_CFG_STRUCT(GPP_E20, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* DDPC_CTRLDATA */ _PAD_CFG_STRUCT(GPP_E21, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(DN_20K)), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E22, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(IOAPIC) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E23, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(DN_20K)), -/* I2S2_SCLK */ _PAD_CFG_STRUCT(GPP_F0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* I2S2_SFRM */ _PAD_CFG_STRUCT(GPP_F1, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* I2S2_TXD */ _PAD_CFG_STRUCT(GPP_F2, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* I2S2_RXD */ _PAD_CFG_STRUCT(GPP_F3, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* I2C2_SDA */ _PAD_CFG_STRUCT(GPP_F4, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8), -/* I2C2_SCL */ _PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8), -/* I2C3_SDA */ _PAD_CFG_STRUCT(GPP_F6, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8), -/* I2C3_SCL */ _PAD_CFG_STRUCT(GPP_F7, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8), -/* I2C4_SDA */ _PAD_CFG_STRUCT(GPP_F8, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8), -/* I2C4_SCL */ _PAD_CFG_STRUCT(GPP_F9, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8), -/* ISH_I2C2_SDA */ _PAD_CFG_STRUCT(GPP_F10, PAD_FUNC(NF2) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8), -/* ISH_I2C2_SCL */ _PAD_CFG_STRUCT(GPP_F11, PAD_FUNC(NF2) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8), -/* EMMC_CMD */ _PAD_CFG_STRUCT(GPP_F12, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F13, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F15, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), -/* EMMC_DATA3 */ _PAD_CFG_STRUCT(GPP_F16, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* EMMC_DATA4 */ _PAD_CFG_STRUCT(GPP_F17, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* EMMC_DATA5 */ _PAD_CFG_STRUCT(GPP_F18, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* EMMC_DATA6 */ _PAD_CFG_STRUCT(GPP_F19, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* EMMC_DATA7 */ _PAD_CFG_STRUCT(GPP_F20, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* EMMC_RCLK */ _PAD_CFG_STRUCT(GPP_F21, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* EMMC_CLK */ _PAD_CFG_STRUCT(GPP_F22, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), 0), -/* SD_CMD */ _PAD_CFG_STRUCT(GPP_G0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SD_DATA0 */ _PAD_CFG_STRUCT(GPP_G1, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SD_DATA1 */ _PAD_CFG_STRUCT(GPP_G2, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SD_DATA2 */ _PAD_CFG_STRUCT(GPP_G3, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SD_DATA3 */ _PAD_CFG_STRUCT(GPP_G4, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SD_CD# */ _PAD_CFG_STRUCT(GPP_G5, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SD_CLK */ _PAD_CFG_STRUCT(GPP_G6, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), +/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), +/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), +/* UART0_RTS# */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), +/* UART0_CTS# */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), +/* UART1_RXD */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), +/* UART1_TXD */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), +/* UART1_RTS# */ PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), +/* UART1_CTS# */ PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), +/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), +/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +/* UART2_RTS# */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), +/* UART2_CTS# */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), +/* SPI1_CS# */ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), +/* SPI1_CLK */ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), +/* SPI1_MISO */ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), +/* SPI1_MOSI */ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), +/* FLASHTRIG */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), +/* ISH_I2C0_SDA */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), +/* ISH_I2C0_SCL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), +/* ISH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), +/* ISH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D9, NONE, DEEP, LEVEL, ACPI), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D10, NONE, DEEP, LEVEL, ACPI), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D11, NONE, DEEP, LEVEL, ACPI), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D12, NONE, DEEP, LEVEL, ACPI), +/* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), +/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), +/* ISH_UART0_RTS# */ PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), +/* ISH_UART0_CTS# */ PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), +/* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), +/* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), +/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), +/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), +/* SPI1_IO2 */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), +/* SPI1_IO3 */ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), +/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), +/* GPIO */ PAD_CFG_GPI_SCI(GPP_E0, NONE, DEEP, EDGE_SINGLE, INVERT), +/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), +/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), +/* GPIO */ PAD_CFG_GPIO_BIDIRECT(GPP_E3, 0, NONE, DEEP, LEVEL, ACPI), +/* SATA_DEVSLP0 */ PAD_CFG_NF(GPP_E4, NONE, PWROK, NF1), +/* GPIO */ PAD_CFG_GPI_SCI(GPP_E5, NONE, PLTRST, EDGE_SINGLE, INVERT), +/* GPIO */ PAD_CFG_GPO(GPP_E6, 0, DEEP), +/* GPIO */ PAD_CFG_GPI_DUAL_ROUTE(GPP_E7, NONE, PLTRST, LEVEL, NONE, IOAPIC, SCI), +/* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), +/* GPIO */ PAD_CFG_GPO(GPP_E9, 0, DEEP), +/* GPIO */ PAD_CFG_TERM_GPO(GPP_E10, 1, DN_20K, DEEP), +/* GPIO */ PAD_CFG_TERM_GPO(GPP_E11, 1, DN_20K, DEEP), +/* GPIO */ PAD_NC(GPP_E12, NONE), +/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), +/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), +/* GPIO */ PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT), +/* GPIO */ PAD_CFG_GPI_SCI(GPP_E16, NONE, PLTRST, LEVEL, INVERT), +/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), +/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1), +/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), +/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1), +/* GPIO */ PAD_CFG_GPI_APIC_LOW(GPP_E22, NONE, DEEP), +/* GPIO */ PAD_CFG_TERM_GPO(GPP_E23, 0, DN_20K, PLTRST), +/* I2S2_SCLK */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), +/* I2S2_SFRM */ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), +/* I2S2_TXD */ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), +/* I2S2_RXD */ PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), +/* I2C2_SDA */ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), +/* I2C2_SCL */ PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1), +/* I2C3_SDA */ PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1), +/* I2C3_SCL */ PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1), +/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), +/* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), +/* ISH_I2C2_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF2), +/* ISH_I2C2_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF2), +/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, DEEP, OFF, ACPI), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, ACPI), +/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), +/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), +/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), +/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), +/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), +/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), +/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), +/* GPIO */ PAD_CFG_GPI_APIC_HIGH(GPP_F23, NONE, DEEP), +/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), +/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), +/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), +/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), +/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), +/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), +/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_G7, NONE, DEEP, OFF, ACPI), };
-#endif +#endif /* __ACPI__ */
-#endif +#endif /* MAINBOARD_GPIO_H */
-
build bot (Jenkins) (Code Review) -
Maxim Polyakov (Code Review)
-
Michael Niewöhner (Code Review)
-
Mimoja (Code Review)
-
Patrick Georgi (Code Review)