110 comments:
File src/mainboard/razer/blade_stealth_kbl/gpio.h:
Patch Set #1, Line 13: /* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 14: /* LAD0 */ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 15: /* LAD1 */ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 16: /* LAD2 */ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 17: /* LAD3 */ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 18: /* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 19: /* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 21: /* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 22: /* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 23: /* CLKOUT_LPC1 */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 26: /* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 27: /* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 28: /* SUS_ACK# */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 29: /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 30: /* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 31: /* ISH_GP0 */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 32: /* ISH_GP1 */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 33: /* ISH_GP2 */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 34: /* ISH_GP3 */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 37: /* CORE_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 38: /* CORE_VID1 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 39: /* VRALERT# */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 42: /* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 43: /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 44: /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 46: /* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 48: /* EXT_PWR_GATE# */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 49: /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 50: /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 57: /* GSPI1_CLK */ PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 58: /* GSPI1_MISO */ PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 59: /* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 61: /* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 62: /* SMBDATA */ PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 64: /* SML0CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 65: /* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 69: /* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 70: /* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 71: /* UART0_RTS# */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 72: /* UART0_CTS# */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 73: /* UART1_RXD */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 74: /* UART1_TXD */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 75: /* UART1_RTS# */ PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 76: /* UART1_CTS# */ PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 77: /* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 78: /* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 79: /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 80: /* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 81: /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 82: /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 83: /* UART2_RTS# */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 84: /* UART2_CTS# */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 85: /* SPI1_CS# */ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 86: /* SPI1_CLK */ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 87: /* SPI1_MISO */ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 88: /* SPI1_MOSI */ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 89: /* FLASHTRIG */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 90: /* ISH_I2C0_SDA */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 91: /* ISH_I2C0_SCL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 92: /* ISH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 93: /* ISH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 98: /* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 99: /* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 100: /* ISH_UART0_RTS# */ PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 101: /* ISH_UART0_CTS# */ PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 102: /* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 103: /* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 104: /* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 105: /* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 106: /* SPI1_IO2 */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 107: /* SPI1_IO3 */ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 108: /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 110: /* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 111: /* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 113: /* SATA_DEVSLP0 */ PAD_CFG_NF(GPP_E4, NONE, PWROK, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 117: /* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 122: /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 123: /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 126: /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 127: /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 128: /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 129: /* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 130: /* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 133: /* I2S2_SCLK */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 134: /* I2S2_SFRM */ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 135: /* I2S2_TXD */ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 136: /* I2S2_RXD */ PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 137: /* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 138: /* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 139: /* I2C3_SDA */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 140: /* I2C3_SCL */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 141: /* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 142: /* I2C4_SCL */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 143: /* ISH_I2C2_SDA */ PAD_CFG_NF(GPP_F10, NONE, DEEP, NF2), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 144: /* ISH_I2C2_SCL */ PAD_CFG_NF(GPP_F11, NONE, DEEP, NF2), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 145: /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 149: /* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 150: /* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 151: /* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 152: /* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 153: /* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 154: /* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 155: /* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 157: /* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 158: /* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 159: /* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 160: /* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 161: /* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 162: /* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
Patch Set #1, Line 163: /* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
line over 96 characters
To view, visit change 43411. To unsubscribe, or for help writing mail filters, visit settings.