HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36080 )
Change subject: src: Remove unused 'include <arch/cpu.h>' ......................................................................
src: Remove unused 'include <arch/cpu.h>'
Change-Id: Iaa236f07aed52ccb8c4839047894a14a9446a109 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/arch/x86/acpi_s3.c M src/arch/x86/include/arch/exception.h M src/arch/x86/include/arch/romstage.h M src/arch/x86/include/arch/stages.h M src/cpu/intel/haswell/bootblock.c M src/cpu/intel/haswell/haswell.h M src/cpu/x86/lapic/apic_timer.c M src/device/oprom/realmode/x86.h M src/drivers/amd/agesa/state_machine.c M src/drivers/intel/fsp1_1/include/fsp/car.h M src/drivers/intel/fsp1_1/include/fsp/romstage.h M src/drivers/intel/fsp1_1/include/fsp/util.h M src/drivers/intel/fsp2_0/include/fsp/util.h M src/include/bootblock_common.h M src/include/console/console.h M src/include/cpu/amd/car.h M src/include/cpu/x86/mtrr.h M src/include/cpu/x86/smm.h M src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c M src/soc/imgtec/pistachio/bootblock.c M src/soc/imgtec/pistachio/monotonic_timer.c M src/soc/intel/baytrail/include/soc/romstage.h M src/soc/intel/baytrail/southcluster.c M src/soc/intel/braswell/acpi.c M src/soc/intel/broadwell/include/soc/romstage.h M src/soc/intel/broadwell/lpc.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/fsp_baytrail/acpi.c M src/soc/intel/quark/include/soc/ramstage.h M src/soc/intel/quark/memmap.c M src/soc/samsung/exynos5420/smp.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/fsp_rangeley/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 35 files changed, 0 insertions(+), 36 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/36080/1
diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index 52f8a20..844364a 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -14,7 +14,6 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> -#include <arch/cpu.h> #include <cbmem.h> #include <commonlib/helpers.h> #include <fallback.h> diff --git a/src/arch/x86/include/arch/exception.h b/src/arch/x86/include/arch/exception.h index df6f9e5..167fdb1 100644 --- a/src/arch/x86/include/arch/exception.h +++ b/src/arch/x86/include/arch/exception.h @@ -28,7 +28,6 @@ #ifndef _ARCH_EXCEPTION_H #define _ARCH_EXCEPTION_H
-#include <arch/cpu.h>
#if CONFIG(IDT_IN_EVERY_STAGE) || ENV_RAMSTAGE asmlinkage void exception_init(void); diff --git a/src/arch/x86/include/arch/romstage.h b/src/arch/x86/include/arch/romstage.h index 15c93f2..86d4e63 100644 --- a/src/arch/x86/include/arch/romstage.h +++ b/src/arch/x86/include/arch/romstage.h @@ -14,7 +14,6 @@ #ifndef __ARCH_ROMSTAGE_H__ #define __ARCH_ROMSTAGE_H__
-#include <arch/cpu.h> #include <stddef.h> #include <stdint.h>
diff --git a/src/arch/x86/include/arch/stages.h b/src/arch/x86/include/arch/stages.h index 3ef3cae..ebecf51 100644 --- a/src/arch/x86/include/arch/stages.h +++ b/src/arch/x86/include/arch/stages.h @@ -14,7 +14,6 @@ #ifndef __ARCH_STAGES_H #define __ARCH_STAGES_H
-#include <arch/cpu.h>
asmlinkage void copy_and_run(void);
diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c index 94e5d36..7653753 100644 --- a/src/cpu/intel/haswell/bootblock.c +++ b/src/cpu/intel/haswell/bootblock.c @@ -12,7 +12,6 @@ */
#include <stdint.h> -#include <arch/cpu.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <arch/io.h> diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 4c67ba8..723e2fc 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -15,7 +15,6 @@ #ifndef _CPU_INTEL_HASWELL_H #define _CPU_INTEL_HASWELL_H
-#include <arch/cpu.h>
/* Haswell CPU types */ #define HASWELL_FAMILY_MOBILE 0x306c0 diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index 58836b5..0c53d8c 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -15,7 +15,6 @@ #include <console/console.h> #include <delay.h> #include <thread.h> -#include <arch/cpu.h> #include <arch/early_variables.h> #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> diff --git a/src/device/oprom/realmode/x86.h b/src/device/oprom/realmode/x86.h index a68b50e..ee14a87 100644 --- a/src/device/oprom/realmode/x86.h +++ b/src/device/oprom/realmode/x86.h @@ -14,7 +14,6 @@ #ifndef __DEVICE_OPROM_REALMODE_X86_H__ #define __DEVICE_OPROM_REALMODE_X86_H__
-#include <arch/cpu.h>
#define REALMODE_BASE ((void *)0x600)
diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c index 750d192..fb78d34 100644 --- a/src/drivers/amd/agesa/state_machine.c +++ b/src/drivers/amd/agesa/state_machine.c @@ -17,7 +17,6 @@ #include <stdint.h> #include <string.h> #include <arch/acpi.h> -#include <arch/cpu.h> #include <bootstate.h> #include <cbfs.h> #include <cbmem.h> diff --git a/src/drivers/intel/fsp1_1/include/fsp/car.h b/src/drivers/intel/fsp1_1/include/fsp/car.h index 3d99fa6..0c1b84d 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/car.h +++ b/src/drivers/intel/fsp1_1/include/fsp/car.h @@ -16,7 +16,6 @@ #ifndef FSP1_1_CAR_H #define FSP1_1_CAR_H
-#include <arch/cpu.h> #include <fsp/api.h> #include <stdint.h>
diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h index 2caceeb..d0a5b60 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h @@ -20,7 +20,6 @@
#include <stddef.h> #include <stdint.h> -#include <arch/cpu.h> #include <memory_info.h> #include <fsp/car.h> #include <fsp/util.h> diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h index 45b8eda..7ec748e 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/util.h +++ b/src/drivers/intel/fsp1_1/include/fsp/util.h @@ -18,7 +18,6 @@ #define FSP1_1_UTIL_H
#include <rules.h> -#include <arch/cpu.h> #include <fsp/api.h> /* Current users expect to get the SoC's FSP definitions by including util.h. */ #include <fsp/soc_binding.h> diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index ef7ecd1..b781c11 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -15,7 +15,6 @@
#include <boot/coreboot_tables.h> #include <commonlib/region.h> -#include <arch/cpu.h> #include <fsp/api.h> #include <fsp/info_header.h> #include <memrange.h> diff --git a/src/include/bootblock_common.h b/src/include/bootblock_common.h index 1081f27..8bf195f 100644 --- a/src/include/bootblock_common.h +++ b/src/include/bootblock_common.h @@ -16,7 +16,6 @@ #ifndef __BOOTBLOCK_COMMON_H #define __BOOTBLOCK_COMMON_H
-#include <arch/cpu.h> #include <main_decl.h> #include <timestamp.h> #include <types.h> diff --git a/src/include/console/console.h b/src/include/console/console.h index 1c2a276..5169207 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -17,7 +17,6 @@ #define CONSOLE_CONSOLE_H_
#include <stdint.h> -#include <arch/cpu.h> #include <console/post_codes.h>
/* console.h is supposed to provide the log levels defined in here: */ diff --git a/src/include/cpu/amd/car.h b/src/include/cpu/amd/car.h index 359fa6b..b13995c 100644 --- a/src/include/cpu/amd/car.h +++ b/src/include/cpu/amd/car.h @@ -1,8 +1,6 @@ #ifndef _CPU_AMD_CAR_H #define _CPU_AMD_CAR_H
-#include <arch/cpu.h> - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); asmlinkage void *post_cache_as_ram(void); asmlinkage void cache_as_ram_new_stack(void); diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 29256c8..e00ccd3 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -4,7 +4,6 @@ #include <commonlib/helpers.h> #ifndef __ASSEMBLER__ #include <cpu/x86/msr.h> -#include <arch/cpu.h> #endif
/* These are the region types */ diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index d8b9efe..48f40be 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -16,7 +16,6 @@ #ifndef CPU_X86_SMM_H #define CPU_X86_SMM_H
-#include <arch/cpu.h> #include <types.h>
#define SMM_DEFAULT_BASE 0x30000 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c index ccea732..214b304 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c @@ -16,7 +16,6 @@
#include "mct_d_gcc.h" #include <stdint.h> -#include <arch/cpu.h>
void _WRMSR(u32 addr, u32 lo, u32 hi) { diff --git a/src/soc/imgtec/pistachio/bootblock.c b/src/soc/imgtec/pistachio/bootblock.c index ac4a740..f603b50 100644 --- a/src/soc/imgtec/pistachio/bootblock.c +++ b/src/soc/imgtec/pistachio/bootblock.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */
-#include <arch/cpu.h> #include <arch/mmu.h> #include <assert.h> #include <stdint.h> diff --git a/src/soc/imgtec/pistachio/monotonic_timer.c b/src/soc/imgtec/pistachio/monotonic_timer.c index bbcd8a1..23c1c39 100644 --- a/src/soc/imgtec/pistachio/monotonic_timer.c +++ b/src/soc/imgtec/pistachio/monotonic_timer.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */
-#include <arch/cpu.h> #include <device/mmio.h> #include <soc/cpu.h> #include <stdint.h> diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h index e86861c..c13c914 100644 --- a/src/soc/intel/baytrail/include/soc/romstage.h +++ b/src/soc/intel/baytrail/include/soc/romstage.h @@ -17,7 +17,6 @@ #define _BAYTRAIL_ROMSTAGE_H_
#include <stdint.h> -#include <arch/cpu.h> #include <soc/mrc_wrapper.h>
void mainboard_fill_mrc_params(struct mrc_params *mp); diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 3c0c07f..da35601 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -20,7 +20,6 @@ #include <device/mmio.h> #include <device/pci_ops.h> #include <arch/acpi.h> -#include <arch/cpu.h> #include <bootstate.h> #include <cbmem.h> #include <console/console.h> diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index dbd2950..f68b7ce 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -18,7 +18,6 @@
#include <arch/acpi.h> #include <arch/acpigen.h> -#include <arch/cpu.h> #include <device/mmio.h> #include <arch/smp/mpspec.h> #include <cbmem.h> diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h index cd37cf6..7d0270f 100644 --- a/src/soc/intel/broadwell/include/soc/romstage.h +++ b/src/soc/intel/broadwell/include/soc/romstage.h @@ -17,7 +17,6 @@ #define _BROADWELL_ROMSTAGE_H_
#include <stdint.h> -#include <arch/cpu.h> #include <soc/pei_data.h>
struct chipset_power_state; diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 2bebcb8..9a560ae 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -21,7 +21,6 @@ #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> #include <pc80/i8259.h> -#include <arch/cpu.h> #include <arch/io.h> #include <device/pci_ops.h> #include <arch/ioapic.h> diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index e969a04..685c6bc 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -19,7 +19,6 @@
#include <arch/acpi.h> #include <arch/acpigen.h> -#include <arch/cpu.h> #include <arch/smp/mpspec.h> #include <cpu/x86/smm.h> #include <string.h> diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c index 59dc6be..acfe8c4 100644 --- a/src/soc/intel/fsp_baytrail/acpi.c +++ b/src/soc/intel/fsp_baytrail/acpi.c @@ -20,7 +20,6 @@ #include <console/console.h> #include <arch/acpi.h> #include <arch/acpigen.h> -#include <arch/cpu.h> #include <cpu/x86/msr.h> #include <cpu/x86/smm.h> #include <cpu/intel/speedstep.h> diff --git a/src/soc/intel/quark/include/soc/ramstage.h b/src/soc/intel/quark/include/soc/ramstage.h index ada8899..b6bb304 100644 --- a/src/soc/intel/quark/include/soc/ramstage.h +++ b/src/soc/intel/quark/include/soc/ramstage.h @@ -17,7 +17,6 @@ #ifndef _SOC_RAMSTAGE_H_ #define _SOC_RAMSTAGE_H_
-#include <arch/cpu.h> #include <device/device.h> #include <soc/QuarkNcSocId.h>
diff --git a/src/soc/intel/quark/memmap.c b/src/soc/intel/quark/memmap.c index b8b8506..60f9843 100644 --- a/src/soc/intel/quark/memmap.c +++ b/src/soc/intel/quark/memmap.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */
-#include <arch/cpu.h> #include <arch/romstage.h> #include <cbmem.h> #include <soc/reg_access.h> diff --git a/src/soc/samsung/exynos5420/smp.c b/src/soc/samsung/exynos5420/smp.c index 5e16063..2c93e45 100644 --- a/src/soc/samsung/exynos5420/smp.c +++ b/src/soc/samsung/exynos5420/smp.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */
-#include <arch/cpu.h> #include <device/mmio.h> #include <soc/cpu.h> #include <soc/power.h> diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 5f0dd8c..266c30f 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -26,7 +26,6 @@ #include <arch/io.h> #include <arch/ioapic.h> #include <arch/acpi.h> -#include <arch/cpu.h> #include <arch/acpigen.h> #include <drivers/intel/gma/i915.h> #include <cpu/x86/smm.h> diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index d12c379..32dbf79 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -27,7 +27,6 @@ #include <device/pci_ops.h> #include <arch/ioapic.h> #include <arch/acpi.h> -#include <arch/cpu.h> #include <cpu/x86/smm.h> #include <string.h> #include <cbmem.h> diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 3657656..fb1a4c2 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -27,7 +27,6 @@ #include <device/pci_ops.h> #include <arch/ioapic.h> #include <arch/acpi.h> -#include <arch/cpu.h> #include <elog.h> #include <arch/acpigen.h> #include <drivers/intel/gma/i915.h> diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 4b44759..660c981 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -26,7 +26,6 @@ #include <arch/io.h> #include <arch/ioapic.h> #include <arch/acpi.h> -#include <arch/cpu.h> #include <cpu/x86/smm.h> #include <cbmem.h> #include <string.h>
Hello Patrick Rudolph, Vanny E, Huang Jin, Lee Leahy, Philipp Deppenwiese, build bot (Jenkins), David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36080
to look at the new patch set (#2).
Change subject: src: Remove unused 'include <arch/cpu.h>' ......................................................................
src: Remove unused 'include <arch/cpu.h>'
Change-Id: Iaa236f07aed52ccb8c4839047894a14a9446a109 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/arch/x86/include/arch/romstage.h M src/cpu/intel/haswell/bootblock.c M src/cpu/intel/haswell/haswell.h M src/cpu/x86/lapic/apic_timer.c M src/drivers/amd/agesa/state_machine.c M src/drivers/intel/fsp1_1/include/fsp/car.h M src/drivers/intel/fsp1_1/include/fsp/romstage.h M src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c M src/soc/imgtec/pistachio/bootblock.c M src/soc/imgtec/pistachio/monotonic_timer.c M src/soc/intel/baytrail/include/soc/romstage.h M src/soc/intel/baytrail/southcluster.c M src/soc/intel/braswell/acpi.c M src/soc/intel/broadwell/include/soc/romstage.h M src/soc/intel/broadwell/lpc.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/fsp_baytrail/acpi.c M src/soc/intel/quark/memmap.c M src/soc/samsung/exynos5420/smp.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/fsp_rangeley/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 23 files changed, 0 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/36080/2
Hello Patrick Rudolph, Vanny E, Huang Jin, Lee Leahy, Philipp Deppenwiese, build bot (Jenkins), David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36080
to look at the new patch set (#3).
Change subject: src: Remove unused 'include <arch/cpu.h>' ......................................................................
src: Remove unused 'include <arch/cpu.h>'
Change-Id: Iaa236f07aed52ccb8c4839047894a14a9446a109 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/arch/x86/include/arch/romstage.h M src/cpu/intel/haswell/bootblock.c M src/cpu/intel/haswell/haswell.h M src/cpu/x86/lapic/apic_timer.c M src/drivers/amd/agesa/state_machine.c M src/drivers/intel/fsp1_1/include/fsp/car.h M src/drivers/intel/fsp1_1/include/fsp/romstage.h M src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c M src/soc/imgtec/pistachio/bootblock.c M src/soc/intel/baytrail/include/soc/romstage.h M src/soc/intel/baytrail/southcluster.c M src/soc/intel/braswell/acpi.c M src/soc/intel/broadwell/include/soc/romstage.h M src/soc/intel/broadwell/lpc.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/fsp_baytrail/acpi.c M src/soc/intel/quark/memmap.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/fsp_rangeley/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 21 files changed, 1 insertion(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/36080/3
Hello Patrick Rudolph, Vanny E, Huang Jin, Lee Leahy, Philipp Deppenwiese, build bot (Jenkins), David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36080
to look at the new patch set (#4).
Change subject: src: Remove unused 'include <arch/cpu.h>' ......................................................................
src: Remove unused 'include <arch/cpu.h>'
Change-Id: Iaa236f07aed52ccb8c4839047894a14a9446a109 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/arch/x86/include/arch/romstage.h M src/cpu/intel/haswell/bootblock.c M src/cpu/intel/haswell/haswell.h M src/cpu/x86/lapic/apic_timer.c M src/drivers/amd/agesa/state_machine.c M src/drivers/intel/fsp1_1/include/fsp/car.h M src/drivers/intel/fsp1_1/include/fsp/romstage.h M src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c M src/soc/intel/baytrail/include/soc/romstage.h M src/soc/intel/baytrail/southcluster.c M src/soc/intel/braswell/acpi.c M src/soc/intel/broadwell/include/soc/romstage.h M src/soc/intel/broadwell/lpc.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/fsp_baytrail/acpi.c M src/soc/intel/quark/memmap.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/fsp_rangeley/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 20 files changed, 1 insertion(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/36080/4
Hello Patrick Rudolph, Vanny E, Huang Jin, Lee Leahy, Philipp Deppenwiese, build bot (Jenkins), David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36080
to look at the new patch set (#7).
Change subject: src: Remove unused 'include <arch/cpu.h>' ......................................................................
src: Remove unused 'include <arch/cpu.h>'
Change-Id: Iaa236f07aed52ccb8c4839047894a14a9446a109 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/arch/x86/include/arch/romstage.h M src/cpu/intel/haswell/bootblock.c M src/cpu/intel/haswell/haswell.h M src/cpu/x86/lapic/apic_timer.c M src/drivers/amd/agesa/state_machine.c M src/drivers/intel/fsp1_1/include/fsp/car.h M src/drivers/intel/fsp1_1/include/fsp/romstage.h M src/soc/intel/baytrail/include/soc/romstage.h M src/soc/intel/baytrail/southcluster.c M src/soc/intel/braswell/acpi.c M src/soc/intel/broadwell/include/soc/romstage.h M src/soc/intel/broadwell/lpc.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/quark/memmap.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 17 files changed, 1 insertion(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/36080/7
Hello Patrick Rudolph, Vanessa Eusebio, Huang Jin, Lee Leahy, Philipp Deppenwiese, build bot (Jenkins), David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36080
to look at the new patch set (#8).
Change subject: src: Remove unused 'include <arch/cpu.h>' ......................................................................
src: Remove unused 'include <arch/cpu.h>'
Change-Id: Iaa236f07aed52ccb8c4839047894a14a9446a109 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/arch/x86/include/arch/romstage.h M src/cpu/intel/haswell/bootblock.c M src/cpu/intel/haswell/haswell.h M src/cpu/x86/lapic/apic_timer.c M src/drivers/amd/agesa/state_machine.c M src/drivers/intel/fsp1_1/include/fsp/car.h M src/drivers/intel/fsp1_1/include/fsp/romstage.h M src/soc/intel/baytrail/include/soc/romstage.h M src/soc/intel/baytrail/southcluster.c M src/soc/intel/braswell/acpi.c M src/soc/intel/broadwell/include/soc/romstage.h M src/soc/intel/broadwell/lpc.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/quark/memmap.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 17 files changed, 1 insertion(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/36080/8
Hello Patrick Rudolph, Vanessa Eusebio, Huang Jin, Lee Leahy, Philipp Deppenwiese, build bot (Jenkins), David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36080
to look at the new patch set (#10).
Change subject: src: Remove unused 'include <arch/cpu.h>' ......................................................................
src: Remove unused 'include <arch/cpu.h>'
Change-Id: Iaa236f07aed52ccb8c4839047894a14a9446a109 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/arch/x86/include/arch/romstage.h M src/cpu/intel/haswell/bootblock.c M src/cpu/intel/haswell/haswell.h M src/cpu/x86/lapic/apic_timer.c M src/drivers/amd/agesa/state_machine.c M src/drivers/intel/fsp1_1/include/fsp/car.h M src/drivers/intel/fsp1_1/include/fsp/romstage.h M src/soc/intel/baytrail/include/soc/romstage.h M src/soc/intel/baytrail/southcluster.c M src/soc/intel/braswell/acpi.c M src/soc/intel/broadwell/include/soc/romstage.h M src/soc/intel/broadwell/lpc.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/quark/memmap.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 17 files changed, 1 insertion(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/36080/10
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36080 )
Change subject: src: Remove unused 'include <arch/cpu.h>' ......................................................................
Patch Set 10: Code-Review+2
Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36080 )
Change subject: src: Remove unused 'include <arch/cpu.h>' ......................................................................
src: Remove unused 'include <arch/cpu.h>'
Change-Id: Iaa236f07aed52ccb8c4839047894a14a9446a109 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/36080 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/arch/x86/include/arch/romstage.h M src/cpu/intel/haswell/bootblock.c M src/cpu/intel/haswell/haswell.h M src/cpu/x86/lapic/apic_timer.c M src/drivers/amd/agesa/state_machine.c M src/drivers/intel/fsp1_1/include/fsp/car.h M src/drivers/intel/fsp1_1/include/fsp/romstage.h M src/soc/intel/baytrail/include/soc/romstage.h M src/soc/intel/baytrail/southcluster.c M src/soc/intel/braswell/acpi.c M src/soc/intel/broadwell/include/soc/romstage.h M src/soc/intel/broadwell/lpc.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/quark/memmap.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 17 files changed, 1 insertion(+), 17 deletions(-)
Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved
diff --git a/src/arch/x86/include/arch/romstage.h b/src/arch/x86/include/arch/romstage.h index 15c93f2..86d4e63 100644 --- a/src/arch/x86/include/arch/romstage.h +++ b/src/arch/x86/include/arch/romstage.h @@ -14,7 +14,6 @@ #ifndef __ARCH_ROMSTAGE_H__ #define __ARCH_ROMSTAGE_H__
-#include <arch/cpu.h> #include <stddef.h> #include <stdint.h>
diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c index 70a4682..e05936f 100644 --- a/src/cpu/intel/haswell/bootblock.c +++ b/src/cpu/intel/haswell/bootblock.c @@ -12,7 +12,6 @@ */
#include <stdint.h> -#include <arch/cpu.h> #include <arch/bootblock.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 4c67ba8..6ffb7e9 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -15,7 +15,7 @@ #ifndef _CPU_INTEL_HASWELL_H #define _CPU_INTEL_HASWELL_H
-#include <arch/cpu.h> +#include <stdint.h>
/* Haswell CPU types */ #define HASWELL_FAMILY_MOBILE 0x306c0 diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index 0b3f691..fbe4f08 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -15,7 +15,6 @@ #include <console/console.h> #include <delay.h> #include <thread.h> -#include <arch/cpu.h> #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h>
diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c index a7255ae..482b615 100644 --- a/src/drivers/amd/agesa/state_machine.c +++ b/src/drivers/amd/agesa/state_machine.c @@ -14,7 +14,6 @@ #include <stdint.h> #include <string.h> #include <arch/acpi.h> -#include <arch/cpu.h> #include <bootstate.h> #include <cbfs.h> #include <cbmem.h> diff --git a/src/drivers/intel/fsp1_1/include/fsp/car.h b/src/drivers/intel/fsp1_1/include/fsp/car.h index 84f2fd8..461f846 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/car.h +++ b/src/drivers/intel/fsp1_1/include/fsp/car.h @@ -14,7 +14,6 @@ #ifndef FSP1_1_CAR_H #define FSP1_1_CAR_H
-#include <arch/cpu.h> #include <fsp/api.h> #include <stdint.h>
diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h index ac8247c..bee49cf 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h @@ -16,7 +16,6 @@
#include <stddef.h> #include <stdint.h> -#include <arch/cpu.h> #include <memory_info.h> #include <fsp/car.h> #include <fsp/util.h> diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h index 16f80b4..ac32305 100644 --- a/src/soc/intel/baytrail/include/soc/romstage.h +++ b/src/soc/intel/baytrail/include/soc/romstage.h @@ -17,7 +17,6 @@ #define _BAYTRAIL_ROMSTAGE_H_
#include <stdint.h> -#include <arch/cpu.h> #include <soc/mrc_wrapper.h>
void mainboard_fill_mrc_params(struct mrc_params *mp); diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 55bef11..bd61f08 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -20,7 +20,6 @@ #include <device/mmio.h> #include <device/pci_ops.h> #include <arch/acpi.h> -#include <arch/cpu.h> #include <bootstate.h> #include <cbmem.h> #include <console/console.h> diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index dbd2950..f68b7ce 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -18,7 +18,6 @@
#include <arch/acpi.h> #include <arch/acpigen.h> -#include <arch/cpu.h> #include <device/mmio.h> #include <arch/smp/mpspec.h> #include <cbmem.h> diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h index cd37cf6..7d0270f 100644 --- a/src/soc/intel/broadwell/include/soc/romstage.h +++ b/src/soc/intel/broadwell/include/soc/romstage.h @@ -17,7 +17,6 @@ #define _BROADWELL_ROMSTAGE_H_
#include <stdint.h> -#include <arch/cpu.h> #include <soc/pei_data.h>
struct chipset_power_state; diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 3392614..007b56b 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -21,7 +21,6 @@ #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> #include <pc80/i8259.h> -#include <arch/cpu.h> #include <arch/io.h> #include <device/pci_ops.h> #include <arch/ioapic.h> diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 48b67b0..163f76a 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -19,7 +19,6 @@
#include <arch/acpi.h> #include <arch/acpigen.h> -#include <arch/cpu.h> #include <arch/smp/mpspec.h> #include <cpu/x86/smm.h> #include <string.h> diff --git a/src/soc/intel/quark/memmap.c b/src/soc/intel/quark/memmap.c index 6cd2c9a..aeba518 100644 --- a/src/soc/intel/quark/memmap.c +++ b/src/soc/intel/quark/memmap.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */
-#include <arch/cpu.h> #include <arch/romstage.h> #include <cbmem.h> #include <soc/reg_access.h> diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index e7b7db8..ef66ca5 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -26,7 +26,6 @@ #include <arch/io.h> #include <arch/ioapic.h> #include <arch/acpi.h> -#include <arch/cpu.h> #include <arch/acpigen.h> #include <drivers/intel/gma/i915.h> #include <cpu/x86/smm.h> diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 2b48eab..324438e 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -27,7 +27,6 @@ #include <device/pci_ops.h> #include <arch/ioapic.h> #include <arch/acpi.h> -#include <arch/cpu.h> #include <elog.h> #include <arch/acpigen.h> #include <drivers/intel/gma/i915.h> diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index c8e91c3..62d8aa6 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -26,7 +26,6 @@ #include <arch/io.h> #include <arch/ioapic.h> #include <arch/acpi.h> -#include <arch/cpu.h> #include <cpu/x86/smm.h> #include <cbmem.h> #include <string.h>
-
HAOUAS Elyes (Code Review) -
Kyösti Mälkki (Code Review)