[M] Change in coreboot[master]: soc/intel/jasperlake: Add configs for USB 3.1 Gen2 EV settings

[Eric Lai (Code Review)]

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76246?usp=email )

Change subject: soc/intel/jasperlake: Add configs for USB 3.1 Gen2 EV settings
......................................................................

soc/intel/jasperlake: Add configs for USB 3.1 Gen2 EV settings

Add configs for USB 3.1 Gen2 electrical validation (EV) settings
so that people can set the EV settings per board in device tree.

BUG=b:285811345
TEST=build coreboot and fsp with enabled fw_debug.
     Flashed to taranza and checked the log.
     All usb configs were set correctly.

Change-Id: Iecd12d3db76b63ad99887dee5991d94d47f138fd
Signed-off-by: Chia-Ling Hou 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76246
Reviewed-by: Eric Lai 
Tested-by: build bot (Jenkins) 
Reviewed-by: Reka Norman 
Reviewed-by: Karthik Ramasubramanian 
---
M src/soc/intel/jasperlake/fsp_params.c
M src/soc/intel/jasperlake/include/soc/usb.h
2 files changed, 60 insertions(+), 0 deletions(-)

Approvals:
  Karthik Ramasubramanian: Looks good to me, approved
  build bot (Jenkins): Verified
  Reka Norman: Looks good to me, approved
  Eric Lai: Looks good to me, approved

diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c
index 1e6731d..50fc136 100644
--- a/src/soc/intel/jasperlake/fsp_params.c
+++ b/src/soc/intel/jasperlake/fsp_params.c
@@ -131,6 +131,27 @@
    		params->Usb3HsioTxDownscaleAmp[i] =
    			config->usb3_ports[i].tx_downscale_amp;
    	}
+		/* Enable USB3 Gen2 */
+		if (config->usb3_ports[i].gen2_tx_rate0_uniq_tran_enable) {
+			params->Usb3HsioTxRate0UniqTranEnable[i] = 1;
+			params->Usb3HsioTxRate0UniqTran[i] =
+				config->usb3_ports[i].gen2_tx_rate0_uniq_tran;
+		}
+		if (config->usb3_ports[i].gen2_tx_rate1_uniq_tran_enable) {
+			params->Usb3HsioTxRate1UniqTranEnable[i] = 1;
+			params->Usb3HsioTxRate1UniqTran[i] =
+				config->usb3_ports[i].gen2_tx_rate1_uniq_tran;
+		}
+		if (config->usb3_ports[i].gen2_tx_rate2_uniq_tran_enable) {
+			params->Usb3HsioTxRate2UniqTranEnable[i] = 1;
+			params->Usb3HsioTxRate2UniqTran[i] =
+				config->usb3_ports[i].gen2_tx_rate2_uniq_tran;
+		}
+		if (config->usb3_ports[i].gen2_tx_rate3_uniq_tran_enable) {
+			params->Usb3HsioTxRate3UniqTranEnable[i] = 1;
+			params->Usb3HsioTxRate3UniqTran[i] =
+				config->usb3_ports[i].gen2_tx_rate3_uniq_tran;
+		}
    }

/* SATA */
diff --git a/src/soc/intel/jasperlake/include/soc/usb.h b/src/soc/intel/jasperlake/include/soc/usb.h
index 69d2d31..2fee395 100644
--- a/src/soc/intel/jasperlake/include/soc/usb.h
+++ b/src/soc/intel/jasperlake/include/soc/usb.h
@@ -119,6 +119,14 @@
    uint8_t ocpin;
    uint8_t tx_de_emp;
    uint8_t tx_downscale_amp;
+	uint8_t gen2_tx_rate0_uniq_tran_enable;
+	uint8_t gen2_tx_rate0_uniq_tran;
+	uint8_t gen2_tx_rate1_uniq_tran_enable;
+	uint8_t gen2_tx_rate1_uniq_tran;
+	uint8_t gen2_tx_rate2_uniq_tran_enable;
+	uint8_t gen2_tx_rate2_uniq_tran;
+	uint8_t gen2_tx_rate3_uniq_tran_enable;
+	uint8_t gen2_tx_rate3_uniq_tran;
 };

#define USB3_PORT_EMPTY { \
@@ -126,6 +134,14 @@
    .ocpin            = OC_SKIP, \
    .tx_de_emp        = 0x00, \
    .tx_downscale_amp = 0x00, \
+	.gen2_tx_rate0_uniq_tran_enable = 0, \
+	.gen2_tx_rate0_uniq_tran = 0x00, \
+	.gen2_tx_rate1_uniq_tran_enable = 0, \
+	.gen2_tx_rate1_uniq_tran = 0x00, \
+	.gen2_tx_rate2_uniq_tran_enable = 0, \
+	.gen2_tx_rate2_uniq_tran = 0x00, \
+	.gen2_tx_rate3_uniq_tran_enable = 0, \
+	.gen2_tx_rate3_uniq_tran = 0x00, \
 }

#define USB3_PORT_DEFAULT(pin) { \
@@ -133,6 +149,29 @@
    .ocpin            = (pin), \
    .tx_de_emp        = 0x0, \
    .tx_downscale_amp = 0x00, \
+	.gen2_tx_rate0_uniq_tran_enable = 0, \
+	.gen2_tx_rate0_uniq_tran = 0x00, \
+	.gen2_tx_rate1_uniq_tran_enable = 0, \
+	.gen2_tx_rate1_uniq_tran = 0x00, \
+	.gen2_tx_rate2_uniq_tran_enable = 0, \
+	.gen2_tx_rate2_uniq_tran = 0x00, \
+	.gen2_tx_rate3_uniq_tran_enable = 0, \
+	.gen2_tx_rate3_uniq_tran = 0x00, \
+}
+
+#define USB3_PORT_GEN2_DEFAULT(pin) { \
+	.enable           = 1, \
+	.ocpin            = (pin), \
+	.tx_de_emp        = 0x0, \
+	.tx_downscale_amp = 0x00, \
+	.gen2_tx_rate0_uniq_tran_enable = 0, \
+	.gen2_tx_rate0_uniq_tran = 0x00, \
+	.gen2_tx_rate1_uniq_tran_enable = 0, \
+	.gen2_tx_rate1_uniq_tran = 0x00, \
+	.gen2_tx_rate2_uniq_tran_enable = 1, \
+	.gen2_tx_rate2_uniq_tran = 0x4C, \
+	.gen2_tx_rate3_uniq_tran_enable = 0, \
+	.gen2_tx_rate3_uniq_tran = 0x00, \
 }

#endif