Change in coreboot[master]: soc/amd/common: Add support to read and set SPI speeds from verstage

[Karthik Ramasubramanian (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Furquan Shaikh, Marshall Dawson, Felix Held.
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58115 )

Change subject: soc/amd/common: Add support to read and set SPI speeds from verstage
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Patch Set 1:

(1 comment)

File src/soc/amd/common/block/psp/psp_efs.c:

https://review.coreboot.org/c/coreboot/+/58115/comment/f6c24ecb_1ca1f529 
PS1, Line 14: efs = rdev_mmap(boot_device_ro(), EFS_OFFSET, sizeof(*efs));
> What is the reasoning for changing this?

This hard-coded EFS address works in x86. PSP maps the SPI ROM at a different memory address and this hard-coded address does not help there.