Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46408 )
Change subject: soc/mediatek/mt8192: ufs: disable refer clk ......................................................................
soc/mediatek/mt8192: ufs: disable refer clk
ufs refer clk is enabled by default, which will cause the UFSHCI hold the SPM signal and lead to suspend fail. Since ufs kernel driver is not built-in, so disable refer clk in coreboot stage.
Signed-off-by: Wenbin Mei wenbin.mei@mediatek.com Signed-off-by: Chaotian Jing chaotian.jing@mediatek.com Change-Id: If11c1b756ad1a0b85f1005f56a6cb4648c687cf0 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/ufs.h M src/soc/mediatek/mt8192/soc.c A src/soc/mediatek/mt8192/ufs.c 5 files changed, 33 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/46408/1
diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 4ce5e6a..7b098e8 100755 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -48,6 +48,7 @@ ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-y += soc.c ramstage-y += devapc.c +ramstage-y += ufs.c ramstage-y += mcupm.c ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h index 19728a3..85eac5b 100644 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -47,6 +47,7 @@ SPI7_BASE = IO_PHYS + 0x0101E000, SSUSB_IPPC_BASE = IO_PHYS + 0x01203e00, SFLASH_REG_BASE = IO_PHYS + 0x01234000, + UFSHCI_BASE = IO_PHYS + 0x01270000, EFUSEC_BASE = IO_PHYS + 0x01C10000, IOCFG_RM_BASE = IO_PHYS + 0x01C20000, IOCFG_BM_BASE = IO_PHYS + 0x01D10000, diff --git a/src/soc/mediatek/mt8192/include/soc/ufs.h b/src/soc/mediatek/mt8192/include/soc/ufs.h new file mode 100644 index 0000000..259aaf4 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/ufs.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_UFS_H +#define SOC_MEDIATEK_MT8192_UFS_H + +#include <device/mmio.h> +#include <soc/addressmap.h> + +void ufs_disable_refclk(void); + +enum ufshci_offset { + REG_UFS_REFCLK_CTRL = 0x144, +}; + +#define UFS_REFCLK_CTRL (ufshci_base + (unsigned long)REG_UFS_REFCLK_CTRL) + +#endif /* SOC_MEDIATEK_MT8192_UFS_H */ diff --git a/src/soc/mediatek/mt8192/soc.c b/src/soc/mediatek/mt8192/soc.c index ba153f2..c865e6f 100644 --- a/src/soc/mediatek/mt8192/soc.c +++ b/src/soc/mediatek/mt8192/soc.c @@ -6,6 +6,7 @@ #include <symbols.h> #include <soc/devapc.h> #include <soc/mcupm.h> +#include <soc/ufs.h>
static void soc_read_resources(struct device *dev) { @@ -16,7 +17,8 @@ { mtk_mmu_disable_l2c_sram(); dapc_init(); - mcupm_init(); + mcupm_init(); + ufs_disable_refclk(); }
static struct device_operations soc_ops = { diff --git a/src/soc/mediatek/mt8192/ufs.c b/src/soc/mediatek/mt8192/ufs.c new file mode 100644 index 0000000..854ef4c --- /dev/null +++ b/src/soc/mediatek/mt8192/ufs.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ufs.h> + +static unsigned long ufshci_base = (unsigned long)UFSHCI_BASE; + +void ufs_disable_refclk(void) +{ + /* disable ref clock to let UFSHCI release SPM signal */ + write32((void*)UFS_REFCLK_CTRL, 0); +}
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46408 )
Change subject: soc/mediatek/mt8192: ufs: disable refer clk ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46408/1/src/soc/mediatek/mt8192/ufs... File src/soc/mediatek/mt8192/ufs.c:
https://review.coreboot.org/c/coreboot/+/46408/1/src/soc/mediatek/mt8192/ufs... PS1, Line 10: write32((void*)UFS_REFCLK_CTRL, 0); "(foo*)" should be "(foo *)"
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46408 )
Change subject: soc/mediatek/mt8192: ufs: disable refer clk ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46408/2/src/soc/mediatek/mt8192/ufs... File src/soc/mediatek/mt8192/ufs.c:
https://review.coreboot.org/c/coreboot/+/46408/2/src/soc/mediatek/mt8192/ufs... PS2, Line 10: write32((void*)UFS_REFCLK_CTRL, 0); "(foo*)" should be "(foo *)"
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46408 )
Change subject: soc/mediatek/mt8192: ufs: disable refer clk ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46408/3/src/soc/mediatek/mt8192/ufs... File src/soc/mediatek/mt8192/ufs.c:
https://review.coreboot.org/c/coreboot/+/46408/3/src/soc/mediatek/mt8192/ufs... PS3, Line 10: write32((void*)UFS_REFCLK_CTRL, 0); "(foo*)" should be "(foo *)"
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46408 )
Change subject: soc/mediatek/mt8192: ufs: disable refer clk ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46408/4/src/soc/mediatek/mt8192/ufs... File src/soc/mediatek/mt8192/ufs.c:
https://review.coreboot.org/c/coreboot/+/46408/4/src/soc/mediatek/mt8192/ufs... PS4, Line 10: write32((void*)UFS_REFCLK_CTRL, 0); "(foo*)" should be "(foo *)"
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46408 )
Change subject: soc/mediatek/mt8192: ufs: disable refer clk ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46408/5/src/soc/mediatek/mt8192/ufs... File src/soc/mediatek/mt8192/ufs.c:
https://review.coreboot.org/c/coreboot/+/46408/5/src/soc/mediatek/mt8192/ufs... PS5, Line 10: write32((void*)UFS_REFCLK_CTRL, 0); "(foo*)" should be "(foo *)"
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46408 )
Change subject: soc/mediatek/mt8192: ufs: disable refer clk ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46408/6/src/soc/mediatek/mt8192/ufs... File src/soc/mediatek/mt8192/ufs.c:
https://review.coreboot.org/c/coreboot/+/46408/6/src/soc/mediatek/mt8192/ufs... PS6, Line 10: write32((void*)UFS_REFCLK_CTRL, 0); "(foo*)" should be "(foo *)"
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46408 )
Change subject: soc/mediatek/mt8192: ufs: disable refer clk ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46408/7/src/soc/mediatek/mt8192/ufs... File src/soc/mediatek/mt8192/ufs.c:
https://review.coreboot.org/c/coreboot/+/46408/7/src/soc/mediatek/mt8192/ufs... PS7, Line 10: write32((void*)UFS_REFCLK_CTRL, 0); "(foo*)" should be "(foo *)"
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46408 )
Change subject: soc/mediatek/mt8192: ufs: disable refer clk ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46408/8/src/soc/mediatek/mt8192/ufs... File src/soc/mediatek/mt8192/ufs.c:
https://review.coreboot.org/c/coreboot/+/46408/8/src/soc/mediatek/mt8192/ufs... PS8, Line 10: write32((void*)UFS_REFCLK_CTRL, 0); "(foo*)" should be "(foo *)"
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46408
to look at the new patch set (#9).
Change subject: soc/mediatek/mt8192: ufs: disable refer clk ......................................................................
soc/mediatek/mt8192: ufs: disable refer clk
ufs refer clk is enabled by default, which will cause the UFSHCI hold the SPM signal and lead to suspend fail. Since ufs kernel driver is not built-in, so disable refer clk in coreboot stage.
Signed-off-by: Wenbin Mei wenbin.mei@mediatek.com Signed-off-by: Chaotian Jing chaotian.jing@mediatek.com Change-Id: If11c1b756ad1a0b85f1005f56a6cb4648c687cf0 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/ufs.h M src/soc/mediatek/mt8192/soc.c A src/soc/mediatek/mt8192/ufs.c 5 files changed, 32 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/46408/9
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46408 )
Change subject: soc/mediatek/mt8192: ufs: disable refer clk ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46408/9/src/soc/mediatek/mt8192/ufs... File src/soc/mediatek/mt8192/ufs.c:
https://review.coreboot.org/c/coreboot/+/46408/9/src/soc/mediatek/mt8192/ufs... PS9, Line 10: write32((void*)UFS_REFCLK_CTRL, 0); "(foo*)" should be "(foo *)"
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46408 )
Change subject: soc/mediatek/mt8192: ufs: disable refer clk ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46408/10/src/soc/mediatek/mt8192/uf... File src/soc/mediatek/mt8192/ufs.c:
https://review.coreboot.org/c/coreboot/+/46408/10/src/soc/mediatek/mt8192/uf... PS10, Line 10: write32((void*)UFS_REFCLK_CTRL, 0); "(foo*)" should be "(foo *)"
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46408 )
Change subject: soc/mediatek/mt8192: ufs: disable refer clk ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46408/11/src/soc/mediatek/mt8192/uf... File src/soc/mediatek/mt8192/ufs.c:
https://review.coreboot.org/c/coreboot/+/46408/11/src/soc/mediatek/mt8192/uf... PS11, Line 10: write32((void*)UFS_REFCLK_CTRL, 0); "(foo*)" should be "(foo *)"
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46408 )
Change subject: soc/mediatek/mt8192: ufs: disable refer clk ......................................................................
Patch Set 13:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46408/13/src/soc/mediatek/mt8192/uf... File src/soc/mediatek/mt8192/ufs.c:
https://review.coreboot.org/c/coreboot/+/46408/13/src/soc/mediatek/mt8192/uf... PS13, Line 10: write32((void*)UFS_REFCLK_CTRL, 0); "(foo*)" should be "(foo *)"
Wenbin Mei has uploaded a new patch set (#14) to the change originally created by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/46408 )
Change subject: soc/mediatek/mt8192: ufs: disable refer clk ......................................................................
soc/mediatek/mt8192: ufs: disable refer clk
ufs refer clk is enabled by default, which will cause the UFSHCI hold the SPM signal and lead to suspend fail. Since ufs kernel driver is not built-in, so disable refer clk in coreboot stage.
Signed-off-by: Wenbin Mei wenbin.mei@mediatek.com Signed-off-by: Chaotian Jing chaotian.jing@mediatek.com Change-Id: If11c1b756ad1a0b85f1005f56a6cb4648c687cf0 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/ufs.h M src/soc/mediatek/mt8192/soc.c A src/soc/mediatek/mt8192/ufs.c 5 files changed, 32 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/46408/14
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Chaotian Jing,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46408
to look at the new patch set (#21).
Change subject: soc/mediatek/mt8192: ufs: disable refer clk ......................................................................
soc/mediatek/mt8192: ufs: disable refer clk
ufs refer clk is enabled by default, which will cause the UFSHCI hold the SPM signal and lead to suspend fail. Since ufs kernel driver is not built-in, so disable refer clk in coreboot stage.
Signed-off-by: Wenbin Mei wenbin.mei@mediatek.com Signed-off-by: Chaotian Jing chaotian.jing@mediatek.com Change-Id: If11c1b756ad1a0b85f1005f56a6cb4648c687cf0 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/ufs.h M src/soc/mediatek/mt8192/soc.c A src/soc/mediatek/mt8192/ufs.c 5 files changed, 32 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/46408/21
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Chaotian Jing,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46408
to look at the new patch set (#25).
Change subject: soc/mediatek/mt8192: ufs: disable refer clk ......................................................................
soc/mediatek/mt8192: ufs: disable refer clk
ufs refer clk is enabled by default, which will cause the UFSHCI hold the SPM signal and lead to suspend fail. Since ufs kernel driver is not built-in, so disable refer clk in coreboot stage.
Signed-off-by: Wenbin Mei wenbin.mei@mediatek.com Signed-off-by: Chaotian Jing chaotian.jing@mediatek.com Change-Id: If11c1b756ad1a0b85f1005f56a6cb4648c687cf0 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/ufs.h M src/soc/mediatek/mt8192/soc.c A src/soc/mediatek/mt8192/ufs.c 5 files changed, 32 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/46408/25
Hello Xi Chen, build bot (Jenkins), Patrick Georgi, Martin Roth, Chaotian Jing,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46408
to look at the new patch set (#31).
Change subject: soc/mediatek/mt8192: ufs: disable refer clk ......................................................................
soc/mediatek/mt8192: ufs: disable refer clk
ufs refer clk is enabled by default, which will cause the UFSHCI hold the SPM signal and lead to suspend fail. Since ufs kernel driver is not built-in, so disable refer clk in coreboot stage.
Signed-off-by: Wenbin Mei wenbin.mei@mediatek.com Signed-off-by: Chaotian Jing chaotian.jing@mediatek.com Change-Id: If11c1b756ad1a0b85f1005f56a6cb4648c687cf0 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/ufs.h M src/soc/mediatek/mt8192/soc.c A src/soc/mediatek/mt8192/ufs.c 5 files changed, 32 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/46408/31
Hello Xi Chen, build bot (Jenkins), Patrick Georgi, Martin Roth, Chaotian Jing,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46408
to look at the new patch set (#35).
Change subject: soc/mediatek/mt8192: ufs: disable refer clk ......................................................................
soc/mediatek/mt8192: ufs: disable refer clk
ufs refer clk is enabled by default, which will cause the UFSHCI hold the SPM signal and lead to suspend fail. Since ufs kernel driver is not built-in, so disable refer clk in coreboot stage.
Signed-off-by: Wenbin Mei wenbin.mei@mediatek.com Signed-off-by: Chaotian Jing chaotian.jing@mediatek.com Change-Id: If11c1b756ad1a0b85f1005f56a6cb4648c687cf0 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/ufs.h M src/soc/mediatek/mt8192/soc.c A src/soc/mediatek/mt8192/ufs.c 5 files changed, 32 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/46408/35
Hello Hung-Te Lin, Xi Chen, build bot (Jenkins), Patrick Georgi, Martin Roth, Chaotian Jing,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46408
to look at the new patch set (#36).
Change subject: soc/mediatek/mt8192: ufs: disable refer clk ......................................................................
soc/mediatek/mt8192: ufs: disable refer clk
ufs refer clk is enabled by default, which will cause the UFSHCI hold the SPM signal and lead to suspend fail. Since ufs kernel driver is not built-in, so disable refer clk in coreboot stage.
Signed-off-by: Wenbin Mei wenbin.mei@mediatek.com Signed-off-by: Chaotian Jing chaotian.jing@mediatek.com Change-Id: If11c1b756ad1a0b85f1005f56a6cb4648c687cf0 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/ufs.h M src/soc/mediatek/mt8192/soc.c A src/soc/mediatek/mt8192/ufs.c 5 files changed, 32 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/46408/36
Hello Hung-Te Lin, Xi Chen, build bot (Jenkins), Patrick Georgi, Martin Roth, Chaotian Jing,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46408
to look at the new patch set (#38).
Change subject: soc/mediatek/mt8192: ufs: disable refer clk ......................................................................
soc/mediatek/mt8192: ufs: disable refer clk
ufs refer clk is enabled by default, which will cause the UFSHCI hold the SPM signal and lead to suspend fail. Since ufs kernel driver is not built-in, so disable refer clk in coreboot stage.
Signed-off-by: Wenbin Mei wenbin.mei@mediatek.com Signed-off-by: Chaotian Jing chaotian.jing@mediatek.com Change-Id: If11c1b756ad1a0b85f1005f56a6cb4648c687cf0 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/ufs.h M src/soc/mediatek/mt8192/soc.c A src/soc/mediatek/mt8192/ufs.c 5 files changed, 32 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/46408/38
Hello Hung-Te Lin, Xi Chen, build bot (Jenkins), Patrick Georgi, Martin Roth, Chaotian Jing,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46408
to look at the new patch set (#39).
Change subject: soc/mediatek/mt8192: ufs: disable refer clk ......................................................................
soc/mediatek/mt8192: ufs: disable refer clk
ufs refer clk is enabled by default, which will cause the UFSHCI hold the SPM signal and lead to suspend fail. Since ufs kernel driver is not built-in, so disable refer clk in coreboot stage.
Signed-off-by: Wenbin Mei wenbin.mei@mediatek.com Signed-off-by: Chaotian Jing chaotian.jing@mediatek.com Change-Id: If11c1b756ad1a0b85f1005f56a6cb4648c687cf0 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/ufs.h M src/soc/mediatek/mt8192/soc.c A src/soc/mediatek/mt8192/ufs.c 5 files changed, 32 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/46408/39
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46408 )
Change subject: soc/mediatek/mt8192: ufs: disable refer clk ......................................................................
Patch Set 41:
(6 comments)
https://review.coreboot.org/c/coreboot/+/46408/41//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46408/41//COMMIT_MSG@9 PS41, Line 9: hold to hold
https://review.coreboot.org/c/coreboot/+/46408/41//COMMIT_MSG@9 PS41, Line 9: ufs refer clk UFS reference clock (refclk)
https://review.coreboot.org/c/coreboot/+/46408/41//COMMIT_MSG@10 PS41, Line 10: ufs UFS
https://review.coreboot.org/c/coreboot/+/46408/41//COMMIT_MSG@10 PS41, Line 10: fail failure
https://review.coreboot.org/c/coreboot/+/46408/41//COMMIT_MSG@11 PS41, Line 11: refer clk Either "reference clock" or "refclk"
https://review.coreboot.org/c/coreboot/+/46408/41//COMMIT_MSG@11 PS41, Line 11: so Remove "so".
Hello Hung-Te Lin, Xi Chen, build bot (Jenkins), Patrick Georgi, Martin Roth, Chaotian Jing,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46408
to look at the new patch set (#42).
Change subject: soc/mediatek/mt8192: ufs: Disable reference clock ......................................................................
soc/mediatek/mt8192: ufs: Disable reference clock
UFS reference clock (refclk) is enabled by default, which will cause the UFSHCI to hold the SPM signal and lead to suspend failure. Since UFS kernel driver is not built-in, disable refclk in coreboot stage.
Signed-off-by: Wenbin Mei wenbin.mei@mediatek.com Signed-off-by: Chaotian Jing chaotian.jing@mediatek.com Change-Id: If11c1b756ad1a0b85f1005f56a6cb4648c687cf0 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/ufs.h M src/soc/mediatek/mt8192/soc.c A src/soc/mediatek/mt8192/ufs.c 5 files changed, 32 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/46408/42
Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46408 )
Change subject: soc/mediatek/mt8192: ufs: Disable reference clock ......................................................................
Patch Set 42:
(6 comments)
https://review.coreboot.org/c/coreboot/+/46408/41//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46408/41//COMMIT_MSG@9 PS41, Line 9: hold
to hold
Done
https://review.coreboot.org/c/coreboot/+/46408/41//COMMIT_MSG@9 PS41, Line 9: ufs refer clk
UFS reference clock (refclk)
Done
https://review.coreboot.org/c/coreboot/+/46408/41//COMMIT_MSG@10 PS41, Line 10: fail
failure
Done
https://review.coreboot.org/c/coreboot/+/46408/41//COMMIT_MSG@10 PS41, Line 10: ufs
UFS
Done
https://review.coreboot.org/c/coreboot/+/46408/41//COMMIT_MSG@11 PS41, Line 11: refer clk
Either "reference clock" or "refclk"
Done
https://review.coreboot.org/c/coreboot/+/46408/41//COMMIT_MSG@11 PS41, Line 11: so
Remove "so".
Done
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46408 )
Change subject: soc/mediatek/mt8192: ufs: Disable reference clock ......................................................................
Patch Set 42: Code-Review+1
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46408 )
Change subject: soc/mediatek/mt8192: ufs: Disable reference clock ......................................................................
Patch Set 42:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46408/42/src/soc/mediatek/mt8192/in... File src/soc/mediatek/mt8192/include/soc/ufs.h:
https://review.coreboot.org/c/coreboot/+/46408/42/src/soc/mediatek/mt8192/in... PS42, Line 15: (unsigned long) not sure why we want to cast as ulong here? I think it'd be better no type-casting, or intptr_t ?
Hello Hung-Te Lin, Xi Chen, build bot (Jenkins), Patrick Georgi, Martin Roth, Chaotian Jing, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46408
to look at the new patch set (#43).
Change subject: soc/mediatek/mt8192: ufs: Disable reference clock ......................................................................
soc/mediatek/mt8192: ufs: Disable reference clock
UFS reference clock (refclk) is enabled by default, which will cause the UFSHCI to hold the SPM signal and lead to suspend failure. Since UFS kernel driver is not built-in, disable refclk in coreboot stage.
Signed-off-by: Wenbin Mei wenbin.mei@mediatek.com Signed-off-by: Chaotian Jing chaotian.jing@mediatek.com Change-Id: If11c1b756ad1a0b85f1005f56a6cb4648c687cf0 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/ufs.h M src/soc/mediatek/mt8192/soc.c A src/soc/mediatek/mt8192/ufs.c 5 files changed, 30 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/46408/43
Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46408 )
Change subject: soc/mediatek/mt8192: ufs: Disable reference clock ......................................................................
Patch Set 43:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46408/42/src/soc/mediatek/mt8192/in... File src/soc/mediatek/mt8192/include/soc/ufs.h:
https://review.coreboot.org/c/coreboot/+/46408/42/src/soc/mediatek/mt8192/in... PS42, Line 15: (unsigned long)
not sure why we want to cast as ulong here? I think it'd be better no type-casting, or intptr_t ?
Done
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46408 )
Change subject: soc/mediatek/mt8192: ufs: Disable reference clock ......................................................................
Patch Set 43: Code-Review+2
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46408 )
Change subject: soc/mediatek/mt8192: ufs: Disable reference clock ......................................................................
Patch Set 43: Code-Review+2
Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46408 )
Change subject: soc/mediatek/mt8192: ufs: Disable reference clock ......................................................................
soc/mediatek/mt8192: ufs: Disable reference clock
UFS reference clock (refclk) is enabled by default, which will cause the UFSHCI to hold the SPM signal and lead to suspend failure. Since UFS kernel driver is not built-in, disable refclk in coreboot stage.
Signed-off-by: Wenbin Mei wenbin.mei@mediatek.com Signed-off-by: Chaotian Jing chaotian.jing@mediatek.com Change-Id: If11c1b756ad1a0b85f1005f56a6cb4648c687cf0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46408 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Hung-Te Lin hungte@chromium.org Reviewed-by: Yu-Ping Wu yupingso@google.com --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/ufs.h M src/soc/mediatek/mt8192/soc.c A src/soc/mediatek/mt8192/ufs.c 5 files changed, 30 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved
diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 2379966..cf09b3c 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -55,6 +55,7 @@ ramstage-y += sspm.c ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c +ramstage-y += ufs.c ramstage-y += ../common/usb.c usb.c
MT8192_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8192 diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h index c9b3907..7660bcc 100644 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -49,6 +49,7 @@ SPI7_BASE = IO_PHYS + 0x0101E000, SSUSB_IPPC_BASE = IO_PHYS + 0x01203e00, SFLASH_REG_BASE = IO_PHYS + 0x01234000, + UFSHCI_BASE = IO_PHYS + 0x01270000, EFUSEC_BASE = IO_PHYS + 0x01C10000, IOCFG_RM_BASE = IO_PHYS + 0x01C20000, I2C_BASE = IO_PHYS + 0x01CB0000, diff --git a/src/soc/mediatek/mt8192/include/soc/ufs.h b/src/soc/mediatek/mt8192/include/soc/ufs.h new file mode 100644 index 0000000..70a30a9 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/ufs.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_UFS_H +#define SOC_MEDIATEK_MT8192_UFS_H + +#include <device/mmio.h> +#include <soc/addressmap.h> + +void ufs_disable_refclk(void); + +enum ufshci_offset { + REG_UFS_REFCLK_CTRL = 0x144, +}; + +#define UFS_REFCLK_CTRL (UFSHCI_BASE + REG_UFS_REFCLK_CTRL) + +#endif /* SOC_MEDIATEK_MT8192_UFS_H */ diff --git a/src/soc/mediatek/mt8192/soc.c b/src/soc/mediatek/mt8192/soc.c index bf9e8e7..8696f34 100644 --- a/src/soc/mediatek/mt8192/soc.c +++ b/src/soc/mediatek/mt8192/soc.c @@ -5,6 +5,7 @@ #include <soc/mcupm.h> #include <soc/mmu_operations.h> #include <soc/sspm.h> +#include <soc/ufs.h> #include <symbols.h>
static void soc_read_resources(struct device *dev) @@ -17,6 +18,7 @@ mtk_mmu_disable_l2c_sram(); mcupm_init(); sspm_init(); + ufs_disable_refclk(); }
static struct device_operations soc_ops = { diff --git a/src/soc/mediatek/mt8192/ufs.c b/src/soc/mediatek/mt8192/ufs.c new file mode 100644 index 0000000..2537fa7 --- /dev/null +++ b/src/soc/mediatek/mt8192/ufs.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ufs.h> + +void ufs_disable_refclk(void) +{ + /* disable ref clock to let UFSHCI release SPM signal */ + write32((void *)UFS_REFCLK_CTRL, 0); +}
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