Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47988 )
Change subject: soc/intel/common/dmi: Add DMI driver support ......................................................................
soc/intel/common/dmi: Add DMI driver support
This is change allows configuring the General Purpose Memory Range(GPMR) register in BIOS to set up the decoding of extended BIOS region in DMI. This driver provides the following functionality: 1. Add a helper function dmi_enable_gpmr which takes as input base, limit and destination ID to configure in general purpose memory range registers. It can ensure that the PCR base address is configured and then set the GPMR registers in the next available free GMPR and enable the decoding. 2. Add helper function get_available_gpmr which returns available free GPMR. 2. This helper function can be utilized by the fast SPI driver to configure the window for the extended BIOS region.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: I34a894e295ecb98fbc4a81282361e851c436a403 --- A src/soc/intel/common/block/dmi/Kconfig A src/soc/intel/common/block/dmi/Makefile.inc A src/soc/intel/common/block/dmi/dmi.c A src/soc/intel/common/block/include/intelblocks/dmi.h M src/soc/intel/common/pch/Kconfig 5 files changed, 88 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/47988/1
diff --git a/src/soc/intel/common/block/dmi/Kconfig b/src/soc/intel/common/block/dmi/Kconfig new file mode 100644 index 0000000..2cc4646 --- /dev/null +++ b/src/soc/intel/common/block/dmi/Kconfig @@ -0,0 +1,5 @@ +config SOC_INTEL_COMMON_BLOCK_DMI + bool + select SOC_INTEL_COMMON_BLOCK_PCR + help + Intel Processor common DMI support diff --git a/src/soc/intel/common/block/dmi/Makefile.inc b/src/soc/intel/common/block/dmi/Makefile.inc new file mode 100644 index 0000000..99a1c18 --- /dev/null +++ b/src/soc/intel/common/block/dmi/Makefile.inc @@ -0,0 +1,10 @@ +ifeq ($(CONFIG_SOC_INTEL_COMMON_BLOCK_DMI), y) + +bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_DMI) += dmi.c +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_DMI) += dmi.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_DMI) += dmi.c +smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_DMI) += dmi.c +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_DMI) += dmi.c +verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_DMI) += dmi.c + +endif diff --git a/src/soc/intel/common/block/dmi/dmi.c b/src/soc/intel/common/block/dmi/dmi.c new file mode 100644 index 0000000..eac86e8 --- /dev/null +++ b/src/soc/intel/common/block/dmi/dmi.c @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <intelblocks/dmi.h> +#include <intelblocks/pcr.h> +#include <soc/pcr_ids.h> + +#define MAX_GPMR_REGS 2 /* 3 GPMR registers */ +#define GPMR_OFFSET(x) (0x277c + (x)*8) +#define GPMR_DID_OFFSET(x) (0x2780 + (x)*8) +#define DMI_PCR_GPMR_BASE_SHIFT 16 +#define DMI_PCR_GPMR_LIMIT_MASK 0xffff0000 +#define DMI_PCR_GPMR_BASE_MASK 0xffff +#define DMI_PCR_GPMR_EN BIT(31) + +/* GPMR Register read given offset */ +static uint32_t gpmr_read32(uint16_t offset) +{ + return pcr_read32(PID_DMI, offset); +} + +/* GPMR Register write given offset and val */ +static void gpmr_write32(uint16_t offset, uint32_t val) +{ + return pcr_write32(PID_DMI, offset, val); +} + +/* Check for available free gpmr */ +static uint32_t get_available_gpmr(void) +{ + int i; + uint32_t val; + + for (i = 0; i <= MAX_GPMR_REGS; i++) { + val = gpmr_read32(GPMR_DID_OFFSET(i)); + if (!(val & DMI_PCR_GPMR_EN)) + return i; + } + printk(BIOS_ERR, "get_available_gpmr: No available free gpmr found \n"); + return -1; +} + +/* Configure GPMR for the given base and size of extended BIOS Region */ +void dmi_enable_gpmr(uint32_t base, uint32_t size, uint32_t dest_id) +{ + uint32_t gpmr_num; + + /* Get available free GPMR */ + gpmr_num = get_available_gpmr(); + + /* Program Range for the given decode window */ + gpmr_write32(GPMR_OFFSET(gpmr_num), + (size & DMI_PCR_GPMR_LIMIT_MASK) | + ((base >> DMI_PCR_GPMR_BASE_SHIFT) & DMI_PCR_GPMR_BASE_MASK)); + + /* Program source decode enable bit and the Destination ID */ + gpmr_write32(GPMR_DID_OFFSET(gpmr_num), dest_id | DMI_PCR_GPMR_EN); +} diff --git a/src/soc/intel/common/block/include/intelblocks/dmi.h b/src/soc/intel/common/block/include/intelblocks/dmi.h new file mode 100644 index 0000000..629d1a6 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/dmi.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_INTEL_COMMON_BLOCK_DMI_H +#define SOC_INTEL_COMMON_BLOCK_DMI_H + +#include <types.h> + +/* + * Takes base, size and destination ID and configures the GPMR + * for accessing the region. + */ +void dmi_enable_gpmr(uint32_t base, uint32_t size, uint32_t dest_id); + +#endif /* SOC_INTEL_COMMON_BLOCK_DMI_H */ diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig index cca65d6..b00fc8b 100644 --- a/src/soc/intel/common/pch/Kconfig +++ b/src/soc/intel/common/pch/Kconfig @@ -19,6 +19,7 @@ select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CSE select SOC_INTEL_COMMON_BLOCK_DSP + select SOC_INTEL_COMMON_BLOCK_DMI select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_GPIO select SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47988 )
Change subject: soc/intel/common/dmi: Add DMI driver support ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/c/coreboot/+/47988/1/src/soc/intel/common/block/... File src/soc/intel/common/block/dmi/dmi.c:
https://review.coreboot.org/c/coreboot/+/47988/1/src/soc/intel/common/block/... PS1, Line 39: printk(BIOS_ERR, "get_available_gpmr: No available free gpmr found \n"); Prefer using '"%s...", __func__' to using 'get_available_gpmr', this function's name, in a string
https://review.coreboot.org/c/coreboot/+/47988/1/src/soc/intel/common/block/... PS1, Line 39: printk(BIOS_ERR, "get_available_gpmr: No available free gpmr found \n"); unnecessary whitespace before a quoted newline
https://review.coreboot.org/c/coreboot/+/47988/1/src/soc/intel/common/block/... File src/soc/intel/common/block/include/intelblocks/dmi.h:
https://review.coreboot.org/c/coreboot/+/47988/1/src/soc/intel/common/block/... PS1, Line 9: * Takes base, size and destination ID and configures the GPMR trailing whitespace
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47988 )
Change subject: soc/intel/common/dmi: Add DMI driver support ......................................................................
Patch Set 1:
(11 comments)
https://review.coreboot.org/c/coreboot/+/47988/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47988/1//COMMIT_MSG@9 PS1, Line 9: is drop "is"
https://review.coreboot.org/c/coreboot/+/47988/1//COMMIT_MSG@10 PS1, Line 10: set up the decoding of extended : BIOS region in DMI GPMR configuration can be used for any decoding. One use case is decoding of extended BIOS region.
https://review.coreboot.org/c/coreboot/+/47988/1//COMMIT_MSG@15 PS1, Line 15: It can ensure that the PCR base address is configured Actually, it is SoC's responsibility to ensure that.
https://review.coreboot.org/c/coreboot/+/47988/1//COMMIT_MSG@20 PS1, Line 20: 2 3
https://review.coreboot.org/c/coreboot/+/47988/1/src/soc/intel/common/block/... File src/soc/intel/common/block/dmi/dmi.c:
https://review.coreboot.org/c/coreboot/+/47988/1/src/soc/intel/common/block/... PS1, Line 8: 2 Comment says 3? For now I think it is fine to put these definitions here. But for a future platform we should evaluate if this is SoC specific or can be used across SoCs. Same with macros below.
https://review.coreboot.org/c/coreboot/+/47988/1/src/soc/intel/common/block/... PS1, Line 11: #define DMI_PCR_GPMR_BASE_SHIFT 16 : #define DMI_PCR_GPMR_LIMIT_MASK 0xffff0000 : #define DMI_PCR_GPMR_BASE_MASK 0xffff : #define DMI_PCR_GPMR_EN BIT(31) Typically fields within a register are defined below it and with a single space before the name.
i.e. #define GPMR_OFFSET(x) (0x277c + (x)*8) #define DMI_PCR_GPMR_LIMIT_MASK 0xffff0000 #define DMI_PCR_GPMR_BASE_SHIFT 16 #define DMI_PCR_GPMR_BASE_MASK 0xffff
#define GPMR_DID_OFFSET(x) (0x2780 + (x)*8) #define DMI_PCR_GPMR_EN BIT(31)
https://review.coreboot.org/c/coreboot/+/47988/1/src/soc/intel/common/block/... PS1, Line 29: uint32_t "int" since in the failed case you are returning -1.
https://review.coreboot.org/c/coreboot/+/47988/1/src/soc/intel/common/block/... PS1, Line 50: Chekc if gpmr_num is not -1.
if (gpmr_num == -1) return;
https://review.coreboot.org/c/coreboot/+/47988/1/src/soc/intel/common/block/... PS1, Line 53: size This is not correct. You will have to calculate limit.
uint32_t limit = base + size - 1;
if (base & ~(DMI_PCR_GPMR_BASE_MASK << DMI_PCR_GPMR_BASE_SHIFT)) { printk(BIOS_ERR, "base is not 64-KiB aligned!\n"); return CB_ERR; }
if (limit & ~DMI_PCR_GPMR_LIMIT_MASK) { printk(BIOS_ERR, "limit does not end on a 64-KiB boundary!\n"); return CB_ERR; }
gpmr_write32(GPMR_OFFSET(gpmr_num), (limit & DMI_PCR_GPMR_LIMIT_MASK) | ((base >> DMI_PCR_GPMR_BASE_SHIFT) & DMI_PCR_GPMR_BASE_MASK));
https://review.coreboot.org/c/coreboot/+/47988/1/src/soc/intel/common/block/... File src/soc/intel/common/block/include/intelblocks/dmi.h:
https://review.coreboot.org/c/coreboot/+/47988/1/src/soc/intel/common/block/... PS1, Line 9: * Takes base, size and destination ID and configures the GPMR
trailing whitespace
Needs to be fixed.
https://review.coreboot.org/c/coreboot/+/47988/1/src/soc/intel/common/block/... PS1, Line 12: void Probably should return enum cb_err to indicate if the GPMR was enabled.
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47988 )
Change subject: soc/intel/common/dmi: Add DMI driver support ......................................................................
Patch Set 1:
(11 comments)
https://review.coreboot.org/c/coreboot/+/47988/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47988/1//COMMIT_MSG@9 PS1, Line 9: is
drop "is"
Ack
https://review.coreboot.org/c/coreboot/+/47988/1//COMMIT_MSG@10 PS1, Line 10: set up the decoding of extended : BIOS region in DMI
GPMR configuration can be used for any decoding. One use case is decoding of extended BIOS region.
Ack
https://review.coreboot.org/c/coreboot/+/47988/1//COMMIT_MSG@15 PS1, Line 15: It can ensure that the PCR base address is configured
Actually, it is SoC's responsibility to ensure that.
Ack
https://review.coreboot.org/c/coreboot/+/47988/1//COMMIT_MSG@20 PS1, Line 20: 2
3
Ack
https://review.coreboot.org/c/coreboot/+/47988/1/src/soc/intel/common/block/... File src/soc/intel/common/block/dmi/dmi.c:
https://review.coreboot.org/c/coreboot/+/47988/1/src/soc/intel/common/block/... PS1, Line 8: 2
Comment says 3? For now I think it is fine to put these definitions here. […]
I was using it as 0-2 (3). I can change it to 3 and do 1-3, let me know. Yes, for future platforms we should move if there are any changes to number of GPMR's.
https://review.coreboot.org/c/coreboot/+/47988/1/src/soc/intel/common/block/... PS1, Line 11: #define DMI_PCR_GPMR_BASE_SHIFT 16 : #define DMI_PCR_GPMR_LIMIT_MASK 0xffff0000 : #define DMI_PCR_GPMR_BASE_MASK 0xffff : #define DMI_PCR_GPMR_EN BIT(31)
Typically fields within a register are defined below it and with a single space before the name. […]
Ack
https://review.coreboot.org/c/coreboot/+/47988/1/src/soc/intel/common/block/... PS1, Line 29: uint32_t
"int" since in the failed case you are returning -1.
Ack
https://review.coreboot.org/c/coreboot/+/47988/1/src/soc/intel/common/block/... PS1, Line 50:
Chekc if gpmr_num is not -1. […]
Ack
https://review.coreboot.org/c/coreboot/+/47988/1/src/soc/intel/common/block/... PS1, Line 53: size
This is not correct. You will have to calculate limit. […]
Agree, I was initially under the impression that size was limit. I understood from your previous comment and the document. I will change this.
https://review.coreboot.org/c/coreboot/+/47988/1/src/soc/intel/common/block/... File src/soc/intel/common/block/include/intelblocks/dmi.h:
https://review.coreboot.org/c/coreboot/+/47988/1/src/soc/intel/common/block/... PS1, Line 9: * Takes base, size and destination ID and configures the GPMR
Needs to be fixed.
Ack
https://review.coreboot.org/c/coreboot/+/47988/1/src/soc/intel/common/block/... PS1, Line 12: void
Probably should return enum cb_err to indicate if the GPMR was enabled.
Ack
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47988 )
Change subject: soc/intel/common/dmi: Add DMI driver support ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47988/1/src/soc/intel/common/block/... File src/soc/intel/common/block/dmi/dmi.c:
https://review.coreboot.org/c/coreboot/+/47988/1/src/soc/intel/common/block/... PS1, Line 8: 2
I was using it as 0-2 (3). I can change it to 3 and do 1-3, let me know. […]
Index can be 0-2, but MAX_ always refers to the actual count. So, it would be better to set this to 3 and use i = 0; i < MAX_GPMR_REGS; i++ below.
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47988 )
Change subject: soc/intel/common/dmi: Add DMI driver support ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47988/1/src/soc/intel/common/block/... File src/soc/intel/common/block/dmi/dmi.c:
https://review.coreboot.org/c/coreboot/+/47988/1/src/soc/intel/common/block/... PS1, Line 8: 2
Index can be 0-2, but MAX_ always refers to the actual count. […]
Sure
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47988
to look at the new patch set (#2).
Change subject: soc/intel/common/dmi: Add DMI driver support ......................................................................
soc/intel/common/dmi: Add DMI driver support
This change allows configuring the General Purpose Memory Range(GPMR) register in BIOS to set up the decoding in DMI.
This driver provides the following functionality: 1. Add a helper function dmi_enable_gpmr which takes as input base, limit and destination ID to configure in general purpose memory range registers and then set the GPMR registers in the next available free GMPR and enable the decoding. 2. Add helper function get_available_gpmr which returns available free GPMR. 3. This helper function can be utilized by the fast SPI driver to configure the window for the extended BIOS region.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: I34a894e295ecb98fbc4a81282361e851c436a403 --- A src/soc/intel/common/block/dmi/Kconfig A src/soc/intel/common/block/dmi/Makefile.inc A src/soc/intel/common/block/dmi/dmi.c A src/soc/intel/common/block/include/intelblocks/dmi.h M src/soc/intel/common/pch/Kconfig 5 files changed, 105 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/47988/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47988 )
Change subject: soc/intel/common/dmi: Add DMI driver support ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47988/2/src/soc/intel/common/block/... File src/soc/intel/common/block/dmi/dmi.c:
https://review.coreboot.org/c/coreboot/+/47988/2/src/soc/intel/common/block/... PS2, Line 68: gpmr_write32(GPMR_OFFSET(gpmr_num),(limit & DMI_PCR_GPMR_LIMIT_MASK) | space required after that ',' (ctx:VxV)
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47988 )
Change subject: soc/intel/common/dmi: Add DMI driver support ......................................................................
Patch Set 2:
(13 comments)
https://review.coreboot.org/c/coreboot/+/47988/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47988/1//COMMIT_MSG@9 PS1, Line 9: is
Ack
done
https://review.coreboot.org/c/coreboot/+/47988/1//COMMIT_MSG@10 PS1, Line 10: set up the decoding of extended : BIOS region in DMI
Ack
done
https://review.coreboot.org/c/coreboot/+/47988/1//COMMIT_MSG@15 PS1, Line 15: It can ensure that the PCR base address is configured
Ack
done
https://review.coreboot.org/c/coreboot/+/47988/1//COMMIT_MSG@20 PS1, Line 20: 2
Ack
done
https://review.coreboot.org/c/coreboot/+/47988/1/src/soc/intel/common/block/... File src/soc/intel/common/block/dmi/dmi.c:
https://review.coreboot.org/c/coreboot/+/47988/1/src/soc/intel/common/block/... PS1, Line 8: 2
Sure
done
https://review.coreboot.org/c/coreboot/+/47988/1/src/soc/intel/common/block/... PS1, Line 11: #define DMI_PCR_GPMR_BASE_SHIFT 16 : #define DMI_PCR_GPMR_LIMIT_MASK 0xffff0000 : #define DMI_PCR_GPMR_BASE_MASK 0xffff : #define DMI_PCR_GPMR_EN BIT(31)
Ack
done
https://review.coreboot.org/c/coreboot/+/47988/1/src/soc/intel/common/block/... PS1, Line 29: uint32_t
Ack
done
https://review.coreboot.org/c/coreboot/+/47988/1/src/soc/intel/common/block/... PS1, Line 39: printk(BIOS_ERR, "get_available_gpmr: No available free gpmr found \n");
unnecessary whitespace before a quoted newline
done
https://review.coreboot.org/c/coreboot/+/47988/1/src/soc/intel/common/block/... PS1, Line 39: printk(BIOS_ERR, "get_available_gpmr: No available free gpmr found \n");
Prefer using '"%s... […]
done
https://review.coreboot.org/c/coreboot/+/47988/1/src/soc/intel/common/block/... PS1, Line 50:
Ack
done
https://review.coreboot.org/c/coreboot/+/47988/1/src/soc/intel/common/block/... PS1, Line 53: size
Agree, I was initially under the impression that size was limit. […]
Done
https://review.coreboot.org/c/coreboot/+/47988/1/src/soc/intel/common/block/... File src/soc/intel/common/block/include/intelblocks/dmi.h:
https://review.coreboot.org/c/coreboot/+/47988/1/src/soc/intel/common/block/... PS1, Line 9: * Takes base, size and destination ID and configures the GPMR
Ack
done
https://review.coreboot.org/c/coreboot/+/47988/1/src/soc/intel/common/block/... PS1, Line 12: void
Ack
done
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47988
to look at the new patch set (#3).
Change subject: soc/intel/common/dmi: Add DMI driver support ......................................................................
soc/intel/common/dmi: Add DMI driver support
This change allows configuring the General Purpose Memory Range(GPMR) register in BIOS to set up the decoding in DMI.
This driver provides the following functionality: 1. Add a helper function dmi_enable_gpmr which takes as input base, limit and destination ID to configure in general purpose memory range registers and then set the GPMR registers in the next available free GMPR and enable the decoding. 2. Add helper function get_available_gpmr which returns available free GPMR. 3. This helper function can be utilized by the fast SPI driver to configure the window for the extended BIOS region.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: I34a894e295ecb98fbc4a81282361e851c436a403 --- A src/soc/intel/common/block/dmi/Kconfig A src/soc/intel/common/block/dmi/Makefile.inc A src/soc/intel/common/block/dmi/dmi.c A src/soc/intel/common/block/include/intelblocks/dmi.h M src/soc/intel/common/pch/Kconfig 5 files changed, 105 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/47988/3
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47988 )
Change subject: soc/intel/common/dmi: Add DMI driver support ......................................................................
Patch Set 4:
(6 comments)
https://review.coreboot.org/c/coreboot/+/47988/4/src/soc/intel/common/block/... File src/soc/intel/common/block/dmi/dmi.c:
https://review.coreboot.org/c/coreboot/+/47988/4/src/soc/intel/common/block/... PS4, Line 8: /* 3 GPMR registers */ Comment can be dropped. Not much helpful.
https://review.coreboot.org/c/coreboot/+/47988/4/src/soc/intel/common/block/... PS4, Line 8: nit: Generally, we use tabs to align all the macros.
https://review.coreboot.org/c/coreboot/+/47988/4/src/soc/intel/common/block/... PS4, Line 10: * spaces around *
https://review.coreboot.org/c/coreboot/+/47988/4/src/soc/intel/common/block/... PS4, Line 15: * spaces around *
https://review.coreboot.org/c/coreboot/+/47988/4/src/soc/intel/common/block/... PS4, Line 56: base + size - 1 We might have to be careful about not overflowing here.
limit = base + (size - 1);
We should also check: if (limit < base) { printk(BIOS_ERR, "..."); return CB_ERR; }
https://review.coreboot.org/c/coreboot/+/47988/4/src/soc/intel/common/block/... PS4, Line 57: limit & ~DMI_PCR_GPMR_LIMIT_MASK Actually, this check needs to ensure that the value is 0xFFFF. Sorry, I had missed this in my comment on earlier patchset.
Example: base 0xf8000000 size 0x200000 then limit = 0xF9FFFFFF. So, when we AND with ~DMI_PCR_GPMR_LIMIT_MASK, it comes out to 0xFFFF. So, the check has to be:
if ((limit & ~DMI_PCR_GPMR_LIMIT_MASK) != 0xFFFF) { }
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47988
to look at the new patch set (#5).
Change subject: soc/intel/common/dmi: Add DMI driver support ......................................................................
soc/intel/common/dmi: Add DMI driver support
This change allows configuring the General Purpose Memory Range(GPMR) register in BIOS to set up the decoding in DMI.
This driver provides the following functionality: 1. Add a helper function dmi_enable_gpmr which takes as input base, limit and destination ID to configure in general purpose memory range registers and then set the GPMR registers in the next available free GMPR and enable the decoding. 2. Add helper function get_available_gpmr which returns available free GPMR. 3. This helper function can be utilized by the fast SPI driver to configure the window for the extended BIOS region.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: I34a894e295ecb98fbc4a81282361e851c436a403 --- A src/soc/intel/common/block/dmi/Kconfig A src/soc/intel/common/block/dmi/Makefile.inc A src/soc/intel/common/block/dmi/dmi.c A src/soc/intel/common/block/include/intelblocks/dmi.h M src/soc/intel/common/pch/Kconfig 5 files changed, 111 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/47988/5
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47988 )
Change subject: soc/intel/common/dmi: Add DMI driver support ......................................................................
Patch Set 5:
(5 comments)
https://review.coreboot.org/c/coreboot/+/47988/4/src/soc/intel/common/block/... File src/soc/intel/common/block/dmi/dmi.c:
https://review.coreboot.org/c/coreboot/+/47988/4/src/soc/intel/common/block/... PS4, Line 8:
nit: Generally, we use tabs to align all the macros.
Done
https://review.coreboot.org/c/coreboot/+/47988/4/src/soc/intel/common/block/... PS4, Line 8: /* 3 GPMR registers */
Comment can be dropped. Not much helpful.
Done
https://review.coreboot.org/c/coreboot/+/47988/4/src/soc/intel/common/block/... PS4, Line 10: *
spaces around *
Done
https://review.coreboot.org/c/coreboot/+/47988/4/src/soc/intel/common/block/... PS4, Line 15: *
spaces around *
Done
https://review.coreboot.org/c/coreboot/+/47988/4/src/soc/intel/common/block/... PS4, Line 56: base + size - 1
We might have to be careful about not overflowing here. […]
Done
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47988
to look at the new patch set (#6).
Change subject: soc/intel/common/dmi: Add DMI driver support ......................................................................
soc/intel/common/dmi: Add DMI driver support
This change allows configuring the General Purpose Memory Range(GPMR) register in BIOS to set up the decoding in DMI.
This driver provides the following functionality: 1. Add a helper function dmi_enable_gpmr which takes as input base, limit and destination ID to configure in general purpose memory range registers and then set the GPMR registers in the next available free GMPR and enable the decoding. 2. Add helper function get_available_gpmr which returns available free GPMR. 3. This helper function can be utilized by the fast SPI driver to configure the window for the extended BIOS region.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: I34a894e295ecb98fbc4a81282361e851c436a403 --- A src/soc/intel/common/block/dmi/Kconfig A src/soc/intel/common/block/dmi/Makefile.inc A src/soc/intel/common/block/dmi/dmi.c A src/soc/intel/common/block/include/intelblocks/dmi.h M src/soc/intel/common/pch/Kconfig 5 files changed, 111 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/47988/6
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47988 )
Change subject: soc/intel/common/dmi: Add DMI driver support ......................................................................
Patch Set 6:
(3 comments)
https://review.coreboot.org/c/coreboot/+/47988/6/src/soc/intel/common/block/... File src/soc/intel/common/block/dmi/dmi.c:
https://review.coreboot.org/c/coreboot/+/47988/6/src/soc/intel/common/block/... PS6, Line 10: #define GPMR_OFFSET(x) (0x277c + (x)* 8) need consistent spacing around '*' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47988/6/src/soc/intel/common/block/... PS6, Line 15: #define GPMR_DID_OFFSET(x) (0x2780 + (x)* 8) need consistent spacing around '*' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47988/6/src/soc/intel/common/block/... PS6, Line 58: if (limit < base){ space required before the open brace '{'
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47988
to look at the new patch set (#7).
Change subject: soc/intel/common/dmi: Add DMI driver support ......................................................................
soc/intel/common/dmi: Add DMI driver support
This change allows configuring the General Purpose Memory Range(GPMR) register in BIOS to set up the decoding in DMI.
This driver provides the following functionality: 1. Add a helper function dmi_enable_gpmr which takes as input base, limit and destination ID to configure in general purpose memory range registers and then set the GPMR registers in the next available free GMPR and enable the decoding. 2. Add helper function get_available_gpmr which returns available free GPMR. 3. This helper function can be utilized by the fast SPI driver to configure the window for the extended BIOS region.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: I34a894e295ecb98fbc4a81282361e851c436a403 --- A src/soc/intel/common/block/dmi/Kconfig A src/soc/intel/common/block/dmi/Makefile.inc A src/soc/intel/common/block/dmi/dmi.c A src/soc/intel/common/block/include/intelblocks/dmi.h M src/soc/intel/common/pch/Kconfig 5 files changed, 111 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/47988/7
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47988 )
Change subject: soc/intel/common/dmi: Add DMI driver support ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47988/4/src/soc/intel/common/block/... File src/soc/intel/common/block/dmi/dmi.c:
https://review.coreboot.org/c/coreboot/+/47988/4/src/soc/intel/common/block/... PS4, Line 57: limit & ~DMI_PCR_GPMR_LIMIT_MASK
Actually, this check needs to ensure that the value is 0xFFFF. […]
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47988 )
Change subject: soc/intel/common/dmi: Add DMI driver support ......................................................................
Patch Set 8: Code-Review+2
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47988 )
Change subject: soc/intel/common/dmi: Add DMI driver support ......................................................................
Patch Set 9:
(4 comments)
https://review.coreboot.org/c/coreboot/+/47988/9/src/soc/intel/common/block/... File src/soc/intel/common/block/dmi/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/47988/9/src/soc/intel/common/block/... PS9, Line 1: ifeq ($(CONFIG_SOC_INTEL_COMMON_BLOCK_DMI), y) not necessary, all of the stages are already guarded with this, though you could also leave this one in and just do `bootblock-y += dmi.c`
https://review.coreboot.org/c/coreboot/+/47988/9/src/soc/intel/common/block/... PS9, Line 6: smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_DMI) += dmi.c is this used in SMM?
https://review.coreboot.org/c/coreboot/+/47988/9/src/soc/intel/common/block/... PS9, Line 8: verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_DMI) += dmi.c or verstage?
https://review.coreboot.org/c/coreboot/+/47988/9/src/soc/intel/common/block/... File src/soc/intel/common/block/dmi/dmi.c:
https://review.coreboot.org/c/coreboot/+/47988/9/src/soc/intel/common/block/... PS9, Line 8: #define MAX_GPMR_REGS 3 : : #define GPMR_OFFSET(x) (0x277c + (x) * 8) : #define DMI_PCR_GPMR_LIMIT_MASK 0xffff0000 : #define DMI_PCR_GPMR_BASE_SHIFT 16 : #define DMI_PCR_GPMR_BASE_MASK 0xffff : : #define GPMR_DID_OFFSET(x) (0x2780 + (x) * 8) : #define DMI_PCR_GPMR_EN BIT(31) Do you mind lining up the right-hand side of these?
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47988 )
Change subject: soc/intel/common/dmi: Add DMI driver support ......................................................................
Patch Set 9:
(3 comments)
https://review.coreboot.org/c/coreboot/+/47988/9/src/soc/intel/common/block/... File src/soc/intel/common/block/dmi/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/47988/9/src/soc/intel/common/block/... PS9, Line 1: ifeq ($(CONFIG_SOC_INTEL_COMMON_BLOCK_DMI), y)
not necessary, all of the stages are already guarded with this, though you could also leave this one […]
Yeah that is a good point. I will fix this.
https://review.coreboot.org/c/coreboot/+/47988/9/src/soc/intel/common/block/... PS9, Line 6: smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_DMI) += dmi.c
is this used in SMM?
No. It was added here so that the linker can decide to optimize it out. I can drop smm and verstage since I don't think we would ever need it there (**famous last words**).
https://review.coreboot.org/c/coreboot/+/47988/9/src/soc/intel/common/block/... File src/soc/intel/common/block/dmi/dmi.c:
https://review.coreboot.org/c/coreboot/+/47988/9/src/soc/intel/common/block/... PS9, Line 8: #define MAX_GPMR_REGS 3 : : #define GPMR_OFFSET(x) (0x277c + (x) * 8) : #define DMI_PCR_GPMR_LIMIT_MASK 0xffff0000 : #define DMI_PCR_GPMR_BASE_SHIFT 16 : #define DMI_PCR_GPMR_BASE_MASK 0xffff : : #define GPMR_DID_OFFSET(x) (0x2780 + (x) * 8) : #define DMI_PCR_GPMR_EN BIT(31)
Do you mind lining up the right-hand side of these?
Srinidhi is OOO. I can fix this.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47988 )
Change subject: soc/intel/common/dmi: Add DMI driver support ......................................................................
Patch Set 9:
(4 comments)
https://review.coreboot.org/c/coreboot/+/47988/9/src/soc/intel/common/block/... File src/soc/intel/common/block/dmi/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/47988/9/src/soc/intel/common/block/... PS9, Line 1: ifeq ($(CONFIG_SOC_INTEL_COMMON_BLOCK_DMI), y)
Yeah that is a good point. I will fix this.
Done
https://review.coreboot.org/c/coreboot/+/47988/9/src/soc/intel/common/block/... PS9, Line 6: smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_DMI) += dmi.c
No. It was added here so that the linker can decide to optimize it out. […]
Done
https://review.coreboot.org/c/coreboot/+/47988/9/src/soc/intel/common/block/... PS9, Line 8: verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_DMI) += dmi.c
or verstage?
Done
https://review.coreboot.org/c/coreboot/+/47988/9/src/soc/intel/common/block/... File src/soc/intel/common/block/dmi/dmi.c:
https://review.coreboot.org/c/coreboot/+/47988/9/src/soc/intel/common/block/... PS9, Line 8: #define MAX_GPMR_REGS 3 : : #define GPMR_OFFSET(x) (0x277c + (x) * 8) : #define DMI_PCR_GPMR_LIMIT_MASK 0xffff0000 : #define DMI_PCR_GPMR_BASE_SHIFT 16 : #define DMI_PCR_GPMR_BASE_MASK 0xffff : : #define GPMR_DID_OFFSET(x) (0x2780 + (x) * 8) : #define DMI_PCR_GPMR_EN BIT(31)
Srinidhi is OOO. I can fix this.
Done
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47988 )
Change subject: soc/intel/common/dmi: Add DMI driver support ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47988/9/src/soc/intel/common/block/... File src/soc/intel/common/block/dmi/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/47988/9/src/soc/intel/common/block/... PS9, Line 6: smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_DMI) += dmi.c
Done
I guess I would rather have SMM opt-in to code rather than opt-out
Furquan Shaikh has uploaded a new patch set (#10) to the change originally created by Srinidhi N Kaushik. ( https://review.coreboot.org/c/coreboot/+/47988 )
Change subject: soc/intel/common/dmi: Add DMI driver support ......................................................................
soc/intel/common/dmi: Add DMI driver support
This change allows configuring the General Purpose Memory Range(GPMR) register in BIOS to set up the decoding in DMI.
This driver provides the following functionality: 1. Add a helper function dmi_enable_gpmr which takes as input base, limit and destination ID to configure in general purpose memory range registers and then set the GPMR registers in the next available free GMPR and enable the decoding. 2. Add helper function get_available_gpmr which returns available free GPMR. 3. This helper function can be utilized by the fast SPI driver to configure the window for the extended BIOS region.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: I34a894e295ecb98fbc4a81282361e851c436a403 --- A src/soc/intel/common/block/dmi/Kconfig A src/soc/intel/common/block/dmi/Makefile.inc A src/soc/intel/common/block/dmi/dmi.c A src/soc/intel/common/block/include/intelblocks/dmi.h M src/soc/intel/common/pch/Kconfig 5 files changed, 108 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/47988/10
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47988 )
Change subject: soc/intel/common/dmi: Add DMI driver support ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47988/9/src/soc/intel/common/block/... File src/soc/intel/common/block/dmi/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/47988/9/src/soc/intel/common/block/... PS9, Line 6: smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_DMI) += dmi.c
I guess I would rather have SMM opt-in to code rather than opt-out
Agreed.
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47988 )
Change subject: soc/intel/common/dmi: Add DMI driver support ......................................................................
Patch Set 10:
(2 comments)
https://review.coreboot.org/c/coreboot/+/47988/9/src/soc/intel/common/block/... File src/soc/intel/common/block/dmi/dmi.c:
https://review.coreboot.org/c/coreboot/+/47988/9/src/soc/intel/common/block/... PS9, Line 52: 64 could use DMI_PCR_GPMR_BASE_MASK instead of hardcoding. not likely to change so it isn't a big deal.
https://review.coreboot.org/c/coreboot/+/47988/9/src/soc/intel/common/block/... PS9, Line 70: -1 could use CB_ERR for this (and the return value in get_available_gpmr) as well
Furquan Shaikh has uploaded a new patch set (#11) to the change originally created by Srinidhi N Kaushik. ( https://review.coreboot.org/c/coreboot/+/47988 )
Change subject: soc/intel/common/dmi: Add DMI driver support ......................................................................
soc/intel/common/dmi: Add DMI driver support
This change allows configuring the General Purpose Memory Range(GPMR) register in BIOS to set up the decoding in DMI.
This driver provides the following functionality: 1. Add a helper function dmi_enable_gpmr which takes as input base, limit and destination ID to configure in general purpose memory range registers and then set the GPMR registers in the next available free GMPR and enable the decoding. 2. Add helper function get_available_gpmr which returns available free GPMR. 3. This helper function can be utilized by the fast SPI driver to configure the window for the extended BIOS region.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: I34a894e295ecb98fbc4a81282361e851c436a403 --- A src/soc/intel/common/block/dmi/Kconfig A src/soc/intel/common/block/dmi/Makefile.inc A src/soc/intel/common/block/dmi/dmi.c A src/soc/intel/common/block/include/intelblocks/dmi.h M src/soc/intel/common/pch/Kconfig 5 files changed, 108 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/47988/11
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47988 )
Change subject: soc/intel/common/dmi: Add DMI driver support ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47988/9/src/soc/intel/common/block/... File src/soc/intel/common/block/dmi/dmi.c:
https://review.coreboot.org/c/coreboot/+/47988/9/src/soc/intel/common/block/... PS9, Line 70: -1
could use CB_ERR for this (and the return value in get_available_gpmr) as well
Done
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47988 )
Change subject: soc/intel/common/dmi: Add DMI driver support ......................................................................
Patch Set 11: Code-Review+2
Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47988 )
Change subject: soc/intel/common/dmi: Add DMI driver support ......................................................................
soc/intel/common/dmi: Add DMI driver support
This change allows configuring the General Purpose Memory Range(GPMR) register in BIOS to set up the decoding in DMI.
This driver provides the following functionality: 1. Add a helper function dmi_enable_gpmr which takes as input base, limit and destination ID to configure in general purpose memory range registers and then set the GPMR registers in the next available free GMPR and enable the decoding. 2. Add helper function get_available_gpmr which returns available free GPMR. 3. This helper function can be utilized by the fast SPI driver to configure the window for the extended BIOS region.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: I34a894e295ecb98fbc4a81282361e851c436a403 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47988 Reviewed-by: Duncan Laurie dlaurie@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- A src/soc/intel/common/block/dmi/Kconfig A src/soc/intel/common/block/dmi/Makefile.inc A src/soc/intel/common/block/dmi/dmi.c A src/soc/intel/common/block/include/intelblocks/dmi.h M src/soc/intel/common/pch/Kconfig 5 files changed, 108 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved
diff --git a/src/soc/intel/common/block/dmi/Kconfig b/src/soc/intel/common/block/dmi/Kconfig new file mode 100644 index 0000000..2cc4646 --- /dev/null +++ b/src/soc/intel/common/block/dmi/Kconfig @@ -0,0 +1,5 @@ +config SOC_INTEL_COMMON_BLOCK_DMI + bool + select SOC_INTEL_COMMON_BLOCK_PCR + help + Intel Processor common DMI support diff --git a/src/soc/intel/common/block/dmi/Makefile.inc b/src/soc/intel/common/block/dmi/Makefile.inc new file mode 100644 index 0000000..7d013c9 --- /dev/null +++ b/src/soc/intel/common/block/dmi/Makefile.inc @@ -0,0 +1,7 @@ +ifeq ($(CONFIG_SOC_INTEL_COMMON_BLOCK_DMI), y) + +bootblock-y += dmi.c +romstage-y += dmi.c +ramstage-y += dmi.c + +endif diff --git a/src/soc/intel/common/block/dmi/dmi.c b/src/soc/intel/common/block/dmi/dmi.c new file mode 100644 index 0000000..1a3a602 --- /dev/null +++ b/src/soc/intel/common/block/dmi/dmi.c @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <intelblocks/dmi.h> +#include <intelblocks/pcr.h> +#include <soc/pcr_ids.h> + +#define MAX_GPMR_REGS 3 + +#define GPMR_OFFSET(x) (0x277c + (x) * 8) +#define DMI_PCR_GPMR_LIMIT_MASK 0xffff0000 +#define DMI_PCR_GPMR_BASE_SHIFT 16 +#define DMI_PCR_GPMR_BASE_MASK 0xffff + +#define GPMR_DID_OFFSET(x) (0x2780 + (x) * 8) +#define DMI_PCR_GPMR_EN BIT(31) + +/* GPMR Register read given offset */ +static uint32_t gpmr_read32(uint16_t offset) +{ + return pcr_read32(PID_DMI, offset); +} + +/* GPMR Register write given offset and val */ +static void gpmr_write32(uint16_t offset, uint32_t val) +{ + return pcr_write32(PID_DMI, offset, val); +} + +/* Check for available free gpmr */ +static int get_available_gpmr(void) +{ + int i; + uint32_t val; + + for (i = 0; i < MAX_GPMR_REGS; i++) { + val = gpmr_read32(GPMR_DID_OFFSET(i)); + if (!(val & DMI_PCR_GPMR_EN)) + return i; + } + printk(BIOS_ERR, "%s: No available free gpmr found\n", __func__); + return CB_ERR; +} + +/* Configure GPMR for the given base and size of extended BIOS Region */ +enum cb_err dmi_enable_gpmr(uint32_t base, uint32_t size, uint32_t dest_id) +{ + int gpmr_num; + uint32_t limit; + + if (base & ~(DMI_PCR_GPMR_BASE_MASK << DMI_PCR_GPMR_BASE_SHIFT)) { + printk(BIOS_ERR, "base is not 64-KiB aligned!\n"); + return CB_ERR; + } + + limit = base + (size - 1); + + if (limit < base) { + printk(BIOS_ERR, "Invalid limit: limit cannot be less than base!\n"); + return CB_ERR; + } + + if ((limit & ~DMI_PCR_GPMR_LIMIT_MASK) != 0xffff) { + printk(BIOS_ERR, "limit does not end on a 64-KiB boundary!\n"); + return CB_ERR; + } + + /* Get available free GPMR */ + gpmr_num = get_available_gpmr(); + if (gpmr_num == CB_ERR) + return CB_ERR; + + /* Program Range for the given decode window */ + gpmr_write32(GPMR_OFFSET(gpmr_num), (limit & DMI_PCR_GPMR_LIMIT_MASK) | + ((base >> DMI_PCR_GPMR_BASE_SHIFT) & DMI_PCR_GPMR_BASE_MASK)); + + /* Program source decode enable bit and the Destination ID */ + gpmr_write32(GPMR_DID_OFFSET(gpmr_num), dest_id | DMI_PCR_GPMR_EN); + + return CB_SUCCESS; +} diff --git a/src/soc/intel/common/block/include/intelblocks/dmi.h b/src/soc/intel/common/block/include/intelblocks/dmi.h new file mode 100644 index 0000000..b771b22 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/dmi.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_INTEL_COMMON_BLOCK_DMI_H +#define SOC_INTEL_COMMON_BLOCK_DMI_H + +#include <types.h> + +/* + * Takes base, size and destination ID and configures the GPMR + * for accessing the region. + */ +enum cb_err dmi_enable_gpmr(uint32_t base, uint32_t size, uint32_t dest_id); + +#endif /* SOC_INTEL_COMMON_BLOCK_DMI_H */ diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig index cca65d6..b00fc8b 100644 --- a/src/soc/intel/common/pch/Kconfig +++ b/src/soc/intel/common/pch/Kconfig @@ -19,6 +19,7 @@ select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CSE select SOC_INTEL_COMMON_BLOCK_DSP + select SOC_INTEL_COMMON_BLOCK_DMI select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_GPIO select SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG
-
build bot (Jenkins) (Code Review) -
Duncan Laurie (Code Review)
-
Furquan Shaikh (Code Review)
-
Srinidhi N Kaushik (Code Review)
-
Tim Wawrzynczak (Code Review)