Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48406 )
Change subject: [WIP] soc/amd: Remove Kconfig BOOTBLOCK_ADDR ......................................................................
[WIP] soc/amd: Remove Kconfig BOOTBLOCK_ADDR
Due the location of X86_RESET_VECTOR, the anchor point for linking the bootblock is at the end, which equals ROMSTAGE_ADDR.
Change-Id: I2d25911582393c9a10fd3afa1a484eda2604d95a Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/root_complex.c 3 files changed, 12 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/48406/1
diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld index e595065..352472e 100644 --- a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld +++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld @@ -10,6 +10,9 @@ #define PSP_SHAREDMEM_DRAM_START(addr) SYMBOL(psp_sharedmem_dram, addr) #define PSP_SHAREDMEM_DRAM_END(addr) SYMBOL(epsp_sharedmem_dram, addr)
+BOOTBLOCK_END = CONFIG_ROMSTAGE_ADDR; +BOOTBLOCK_ADDR = BOOTBLOCK_END - CONFIG_C_ENV_BOOTBLOCK_SIZE; + /* * * +--------------------------------+ @@ -31,11 +34,11 @@ * +--------------------------------+ FSP_M_ADDR * | romstage | * | (ROMSTAGE_SIZE) | - * +--------------------------------+ ROMSTAGE_ADDR - * | | X86_RESET_VECTOR = BOOTBLOCK_ADDR + C_ENV_BOOTBLOCK_SIZE - 0x10 + * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END + * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 * | bootblock | * | (C_ENV_BOOTBLOCK_SIZE) | - * +--------------------------------+ BOOTBLOCK_ADDR + * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE * | Unused hole | * +--------------------------------+ * | FMAP cache (FMAP_SIZE) | @@ -84,8 +87,8 @@ #if CONFIG(VBOOT) PSP_SHAREDMEM_DRAM_END(CONFIG_PSP_SHAREDMEM_BASE + CONFIG_PSP_SHAREDMEM_SIZE) #endif - _ = ASSERT(CONFIG_BOOTBLOCK_ADDR == ((CONFIG_BOOTBLOCK_ADDR + 0xFFFF) & 0xFFFF0000), "Bootblock must be 16 bit aligned"); - BOOTBLOCK(CONFIG_BOOTBLOCK_ADDR, CONFIG_C_ENV_BOOTBLOCK_SIZE) + _ = ASSERT(BOOTBLOCK_END == ((BOOTBLOCK_END + 0xFFFF) & 0xFFFF0000), "Bootblock end must be 16 bit aligned"); + BOOTBLOCK(BOOTBLOCK_ADDR, CONFIG_C_ENV_BOOTBLOCK_SIZE) ROMSTAGE(CONFIG_ROMSTAGE_ADDR, CONFIG_ROMSTAGE_SIZE) REGION(fspm, CONFIG_FSP_M_ADDR, CONFIG_FSP_M_SIZE, 1) #if CONFIG(VBOOT_SEPARATE_VERSTAGE) @@ -107,7 +110,7 @@ _TOO_LOW = _X86_RESET_VECTOR - 0xfff0; _bogus = ASSERT(_start16bit >= _TOO_LOW, "_start16bit too low. Please report.");
- . = CONFIG_BOOTBLOCK_ADDR + CONFIG_C_ENV_BOOTBLOCK_SIZE - 0x10; + . = BOOTBLOCK_END - 0x10; _X86_RESET_VECTOR = .; .reset . : { *(.reset); diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index fcb7ddb..bd9964b 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -120,12 +120,6 @@ help Increase this value if preram cbmem console is getting truncated
-config BOOTBLOCK_ADDR - hex - default 0x2030000 - help - Sets the address in DRAM where bootblock should be loaded. - config C_ENV_BOOTBLOCK_SIZE hex default 0x10000 diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index 259419c..7ca44b0 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -77,11 +77,11 @@ * +--------------------------------+ FSP_M_ADDR * | romstage | * | (ROMSTAGE_SIZE) | - * +--------------------------------+ ROMSTAGE_ADDR - * | | X86_RESET_VECTOR = BOOTBLOCK_ADDR + C_ENV_BOOTBLOCK_SIZE - 0x10 + * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END + * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 * | bootblock | * | (C_ENV_BOOTBLOCK_SIZE) | - * +--------------------------------+ BOOTBLOCK_ADDR + * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE * | Unused hole | * | (86KiB) | * +--------------------------------+
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48406 )
Change subject: [WIP] soc/amd: Remove Kconfig BOOTBLOCK_ADDR ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/48406/1/src/soc/amd/picasso/root_co... File src/soc/amd/picasso/root_complex.c:
https://review.coreboot.org/c/coreboot/+/48406/1/src/soc/amd/picasso/root_co... PS1, Line 81: * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 line over 96 characters
https://review.coreboot.org/c/coreboot/+/48406/1/src/soc/amd/picasso/root_co... PS1, Line 84: * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE line over 96 characters
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48406 )
Change subject: [WIP] soc/amd: Remove Kconfig BOOTBLOCK_ADDR ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/48406/2/src/soc/amd/picasso/root_co... File src/soc/amd/picasso/root_complex.c:
https://review.coreboot.org/c/coreboot/+/48406/2/src/soc/amd/picasso/root_co... PS2, Line 81: * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 line over 96 characters
https://review.coreboot.org/c/coreboot/+/48406/2/src/soc/amd/picasso/root_co... PS2, Line 84: * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE line over 96 characters
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48406 )
Change subject: [WIP] soc/amd: Remove Kconfig BOOTBLOCK_ADDR ......................................................................
Patch Set 2:
as a test i set the bootblock size to 0x8000, so that the beginning doesn't fall on a 64k boundary and the resulting image still booted, so this seems correct to me. the kconfig part also needs to be applied to cezanne
Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Julius Werner, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48406
to look at the new patch set (#3).
Change subject: soc/amd: Remove Kconfig BOOTBLOCK_ADDR ......................................................................
soc/amd: Remove Kconfig BOOTBLOCK_ADDR
Due the location of X86_RESET_VECTOR, the anchor point for linking the bootblock is at the end, which equals ROMSTAGE_ADDR.
Change-Id: I2d25911582393c9a10fd3afa1a484eda2604d95a Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/root_complex.c 4 files changed, 12 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/48406/3
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48406 )
Change subject: soc/amd: Remove Kconfig BOOTBLOCK_ADDR ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/48406/3/src/soc/amd/picasso/root_co... File src/soc/amd/picasso/root_complex.c:
https://review.coreboot.org/c/coreboot/+/48406/3/src/soc/amd/picasso/root_co... PS3, Line 81: * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 line over 96 characters
https://review.coreboot.org/c/coreboot/+/48406/3/src/soc/amd/picasso/root_co... PS3, Line 84: * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE line over 96 characters
Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48406 )
Change subject: soc/amd: Remove Kconfig BOOTBLOCK_ADDR ......................................................................
Patch Set 3: Code-Review+2
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48406 )
Change subject: soc/amd: Remove Kconfig BOOTBLOCK_ADDR ......................................................................
Patch Set 3: Code-Review+2
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48406 )
Change subject: soc/amd: Remove Kconfig BOOTBLOCK_ADDR ......................................................................
soc/amd: Remove Kconfig BOOTBLOCK_ADDR
Due the location of X86_RESET_VECTOR, the anchor point for linking the bootblock is at the end, which equals ROMSTAGE_ADDR.
Change-Id: I2d25911582393c9a10fd3afa1a484eda2604d95a Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/48406 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Marshall Dawson marshalldawson3rd@gmail.com Reviewed-by: Felix Held felix-coreboot@felixheld.de --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/root_complex.c 4 files changed, 12 insertions(+), 21 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Marshall Dawson: Looks good to me, approved
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index d2badc9..fe248c6 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -47,12 +47,6 @@ help Increase this value if preram cbmem console is getting truncated
-config BOOTBLOCK_ADDR - hex - default 0x2030000 - help - Sets the address in DRAM where bootblock should be loaded. - config C_ENV_BOOTBLOCK_SIZE hex default 0x10000 diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld index dae69d0..f702b4b 100644 --- a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld +++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld @@ -10,6 +10,9 @@ #define PSP_SHAREDMEM_DRAM_START(addr) SYMBOL(psp_sharedmem_dram, addr) #define PSP_SHAREDMEM_DRAM_END(addr) SYMBOL(epsp_sharedmem_dram, addr)
+BOOTBLOCK_END = CONFIG_ROMSTAGE_ADDR; +BOOTBLOCK_ADDR = BOOTBLOCK_END - CONFIG_C_ENV_BOOTBLOCK_SIZE; + /* * * +--------------------------------+ @@ -31,11 +34,11 @@ * +--------------------------------+ FSP_M_ADDR * | romstage | * | (ROMSTAGE_SIZE) | - * +--------------------------------+ ROMSTAGE_ADDR - * | | X86_RESET_VECTOR = BOOTBLOCK_ADDR + C_ENV_BOOTBLOCK_SIZE - 0x10 + * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END + * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 * | bootblock | * | (C_ENV_BOOTBLOCK_SIZE) | - * +--------------------------------+ BOOTBLOCK_ADDR + * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE * | Unused hole | * +--------------------------------+ * | FMAP cache (FMAP_SIZE) | @@ -84,8 +87,8 @@ #if CONFIG(VBOOT) PSP_SHAREDMEM_DRAM_END(CONFIG_PSP_SHAREDMEM_BASE + CONFIG_PSP_SHAREDMEM_SIZE) #endif - _ = ASSERT(CONFIG_BOOTBLOCK_ADDR == ((CONFIG_BOOTBLOCK_ADDR + 0xFFFF) & 0xFFFF0000), "Bootblock must be 16 bit aligned"); - BOOTBLOCK(CONFIG_BOOTBLOCK_ADDR, CONFIG_C_ENV_BOOTBLOCK_SIZE) + _ = ASSERT(BOOTBLOCK_END == ((BOOTBLOCK_END + 0xFFFF) & 0xFFFF0000), "Bootblock end must be 16 bit aligned"); + BOOTBLOCK(BOOTBLOCK_ADDR, CONFIG_C_ENV_BOOTBLOCK_SIZE) ROMSTAGE(CONFIG_ROMSTAGE_ADDR, CONFIG_ROMSTAGE_SIZE) REGION(fspm, CONFIG_FSP_M_ADDR, CONFIG_FSP_M_SIZE, 1) #if CONFIG(VBOOT_SEPARATE_VERSTAGE) @@ -107,7 +110,7 @@ _TOO_LOW = _X86_RESET_VECTOR - 0xfff0; _bogus = ASSERT(_start16bit >= _TOO_LOW, "_start16bit too low. Please report.");
- . = CONFIG_BOOTBLOCK_ADDR + CONFIG_C_ENV_BOOTBLOCK_SIZE - 0x10; + . = BOOTBLOCK_END - 0x10; _X86_RESET_VECTOR = .; .reset . : { *(.reset); diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index fcb7ddb..bd9964b 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -120,12 +120,6 @@ help Increase this value if preram cbmem console is getting truncated
-config BOOTBLOCK_ADDR - hex - default 0x2030000 - help - Sets the address in DRAM where bootblock should be loaded. - config C_ENV_BOOTBLOCK_SIZE hex default 0x10000 diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index 259419c..7ca44b0 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -77,11 +77,11 @@ * +--------------------------------+ FSP_M_ADDR * | romstage | * | (ROMSTAGE_SIZE) | - * +--------------------------------+ ROMSTAGE_ADDR - * | | X86_RESET_VECTOR = BOOTBLOCK_ADDR + C_ENV_BOOTBLOCK_SIZE - 0x10 + * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END + * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 * | bootblock | * | (C_ENV_BOOTBLOCK_SIZE) | - * +--------------------------------+ BOOTBLOCK_ADDR + * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE * | Unused hole | * | (86KiB) | * +--------------------------------+
-
build bot (Jenkins) (Code Review) -
Felix Held (Code Review)
-
Kyösti Mälkki (Code Review)
-
Marshall Dawson (Code Review)