Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30528
Change subject: sb/intel/*: Use common files for PCIe ACPI ......................................................................
sb/intel/*: Use common files for PCIe ACPI
The result is that i82801{g,i,j} now use the correct _PRT table for their root port number.
Change-Id: I92bba3c669f3e6a44a42e19a88a33dfcfc2b9b42 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/southbridge/intel/i82801gx/acpi/ich7.asl D src/southbridge/intel/i82801gx/acpi/pcie.asl M src/southbridge/intel/i82801ix/acpi/ich9.asl D src/southbridge/intel/i82801ix/acpi/pcie.asl D src/southbridge/intel/i82801ix/acpi/pcie_port.asl M src/southbridge/intel/i82801jx/acpi/ich10.asl D src/southbridge/intel/i82801jx/acpi/pcie.asl D src/southbridge/intel/i82801jx/acpi/pcie_port.asl M src/southbridge/intel/lynxpoint/acpi/pch.asl D src/southbridge/intel/lynxpoint/acpi/pcie.asl D src/southbridge/intel/lynxpoint/acpi/pcie_port.asl 11 files changed, 4 insertions(+), 841 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/30528/1
diff --git a/src/southbridge/intel/i82801gx/acpi/ich7.asl b/src/southbridge/intel/i82801gx/acpi/ich7.asl index c28f4b9..38ca483 100644 --- a/src/southbridge/intel/i82801gx/acpi/ich7.asl +++ b/src/southbridge/intel/i82801gx/acpi/ich7.asl @@ -163,7 +163,7 @@ #include "audio.asl"
// PCI Express Ports -#include "pcie.asl" +#include <southbridge/intel/common/acpi/pcie.asl>
// USB #include "usb.asl" diff --git a/src/southbridge/intel/i82801gx/acpi/pcie.asl b/src/southbridge/intel/i82801gx/acpi/pcie.asl deleted file mode 100644 index 3c644e2..0000000 --- a/src/southbridge/intel/i82801gx/acpi/pcie.asl +++ /dev/null @@ -1,179 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Intel i82801G PCIe support */ - -// PCI Express Ports - -Device (RP01) -{ - NAME(_ADR, 0x001c0000) // FIXME: Have a macro for PCI Devices -> ACPI notation? - //#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 16 }, - Package() { 0x0000ffff, 1, 0, 17 }, - Package() { 0x0000ffff, 2, 0, 18 }, - Package() { 0x0000ffff, 3, 0, 19 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 1, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 2, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 3, _SB.PCI0.LPCB.LNKD, 0 } - }) - - } - - } -} - -Device (RP02) -{ - NAME(_ADR, 0x001c0001) // FIXME: Have a macro for PCI Devices -> ACPI notation? - //#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 17 }, - Package() { 0x0000ffff, 1, 0, 18 }, - Package() { 0x0000ffff, 2, 0, 19 }, - Package() { 0x0000ffff, 3, 0, 16 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 1, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 2, _SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 3, _SB.PCI0.LPCB.LNKA, 0 } - }) - - } - - } -} - - -Device (RP03) -{ - NAME(_ADR, 0x001c0002) // FIXME: Have a macro for PCI Devices -> ACPI notation? - //#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 18 }, - Package() { 0x0000ffff, 1, 0, 19 }, - Package() { 0x0000ffff, 2, 0, 16 }, - Package() { 0x0000ffff, 3, 0, 17 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 1, _SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 2, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 3, _SB.PCI0.LPCB.LNKB, 0 } - }) - - } - - } -} - - -Device (RP04) -{ - NAME(_ADR, 0x001c0003) // FIXME: Have a macro for PCI Devices -> ACPI notation? - //#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 19 }, - Package() { 0x0000ffff, 1, 0, 16 }, - Package() { 0x0000ffff, 2, 0, 17 }, - Package() { 0x0000ffff, 3, 0, 18 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, _SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 1, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 2, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 3, _SB.PCI0.LPCB.LNKC, 0 } - }) - - } - - } -} - - -Device (RP05) -{ - NAME(_ADR, 0x001c0004) // FIXME: Have a macro for PCI Devices -> ACPI notation? - //#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 16 }, - Package() { 0x0000ffff, 1, 0, 17 }, - Package() { 0x0000ffff, 2, 0, 18 }, - Package() { 0x0000ffff, 3, 0, 19 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 1, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 2, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 3, _SB.PCI0.LPCB.LNKD, 0 } - }) - - } - - } -} - - -Device (RP06) -{ - NAME(_ADR, 0x001c0005) // FIXME: Have a macro for PCI Devices -> ACPI notation? - //#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 17 }, - Package() { 0x0000ffff, 1, 0, 18 }, - Package() { 0x0000ffff, 2, 0, 19 }, - Package() { 0x0000ffff, 3, 0, 16 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 1, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 2, _SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 3, _SB.PCI0.LPCB.LNKA, 0 } - }) - - } - - } -} diff --git a/src/southbridge/intel/i82801ix/acpi/ich9.asl b/src/southbridge/intel/i82801ix/acpi/ich9.asl index 78d1f53..d155d15 100644 --- a/src/southbridge/intel/i82801ix/acpi/ich9.asl +++ b/src/southbridge/intel/i82801ix/acpi/ich9.asl @@ -168,7 +168,7 @@ #include "audio.asl"
// PCI Express Ports -#include "pcie.asl" +#include <southbridge/intel/common/acpi/pcie.asl>
// USB #include "usb.asl" diff --git a/src/southbridge/intel/i82801ix/acpi/pcie.asl b/src/southbridge/intel/i82801ix/acpi/pcie.asl deleted file mode 100644 index b484064..0000000 --- a/src/southbridge/intel/i82801ix/acpi/pcie.asl +++ /dev/null @@ -1,179 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Intel i82801G PCIe support */ - -// PCI Express Ports - -Device (RP01) -{ - NAME(_ADR, 0x001c0000) // FIXME: Have a macro for PCI Devices -> ACPI notation? -#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 16 }, - Package() { 0x0000ffff, 1, 0, 17 }, - Package() { 0x0000ffff, 2, 0, 18 }, - Package() { 0x0000ffff, 3, 0, 19 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 1, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 2, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 3, _SB.PCI0.LPCB.LNKD, 0 } - }) - - } - - } -} - -Device (RP02) -{ - NAME(_ADR, 0x001c0001) // FIXME: Have a macro for PCI Devices -> ACPI notation? -#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 17 }, - Package() { 0x0000ffff, 1, 0, 18 }, - Package() { 0x0000ffff, 2, 0, 19 }, - Package() { 0x0000ffff, 3, 0, 16 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 1, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 2, _SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 3, _SB.PCI0.LPCB.LNKA, 0 } - }) - - } - - } -} - - -Device (RP03) -{ - NAME(_ADR, 0x001c0002) // FIXME: Have a macro for PCI Devices -> ACPI notation? -#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 18 }, - Package() { 0x0000ffff, 1, 0, 19 }, - Package() { 0x0000ffff, 2, 0, 16 }, - Package() { 0x0000ffff, 3, 0, 17 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 1, _SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 2, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 3, _SB.PCI0.LPCB.LNKB, 0 } - }) - - } - - } -} - - -Device (RP04) -{ - NAME(_ADR, 0x001c0003) // FIXME: Have a macro for PCI Devices -> ACPI notation? -#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 19 }, - Package() { 0x0000ffff, 1, 0, 16 }, - Package() { 0x0000ffff, 2, 0, 17 }, - Package() { 0x0000ffff, 3, 0, 18 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, _SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 1, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 2, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 3, _SB.PCI0.LPCB.LNKC, 0 } - }) - - } - - } -} - - -Device (RP05) -{ - NAME(_ADR, 0x001c0004) // FIXME: Have a macro for PCI Devices -> ACPI notation? -#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 16 }, - Package() { 0x0000ffff, 1, 0, 17 }, - Package() { 0x0000ffff, 2, 0, 18 }, - Package() { 0x0000ffff, 3, 0, 19 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 1, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 2, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 3, _SB.PCI0.LPCB.LNKD, 0 } - }) - - } - - } -} - - -Device (RP06) -{ - NAME(_ADR, 0x001c0005) // FIXME: Have a macro for PCI Devices -> ACPI notation? -#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 17 }, - Package() { 0x0000ffff, 1, 0, 18 }, - Package() { 0x0000ffff, 2, 0, 19 }, - Package() { 0x0000ffff, 3, 0, 16 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 1, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 2, _SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 3, _SB.PCI0.LPCB.LNKA, 0 } - }) - - } - - } -} diff --git a/src/southbridge/intel/i82801ix/acpi/pcie_port.asl b/src/southbridge/intel/i82801ix/acpi/pcie_port.asl deleted file mode 100644 index 4e04ab2..0000000 --- a/src/southbridge/intel/i82801ix/acpi/pcie_port.asl +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The Chromium OS Authors. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Included in each PCIe Root Port device */ - -OperationRegion (RPCS, PCI_Config, 0x00, 0xFF) -Field (RPCS, AnyAcc, NoLock, Preserve) -{ - Offset (0x4c), // Link Capabilities - , 24, - RPPN, 8, // Root Port Number - Offset (0x5A), - , 3, - PDC, 1, - Offset (0xDF), - , 6, - HPCS, 1, -} diff --git a/src/southbridge/intel/i82801jx/acpi/ich10.asl b/src/southbridge/intel/i82801jx/acpi/ich10.asl index b7d8a33..200dfb5 100644 --- a/src/southbridge/intel/i82801jx/acpi/ich10.asl +++ b/src/southbridge/intel/i82801jx/acpi/ich10.asl @@ -167,7 +167,7 @@ #include "audio.asl"
// PCI Express Ports -#include "pcie.asl" +#include <southbridge/intel/common/acpi/pcie.asl>
// USB #include "usb.asl" diff --git a/src/southbridge/intel/i82801jx/acpi/pcie.asl b/src/southbridge/intel/i82801jx/acpi/pcie.asl deleted file mode 100644 index b484064..0000000 --- a/src/southbridge/intel/i82801jx/acpi/pcie.asl +++ /dev/null @@ -1,179 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Intel i82801G PCIe support */ - -// PCI Express Ports - -Device (RP01) -{ - NAME(_ADR, 0x001c0000) // FIXME: Have a macro for PCI Devices -> ACPI notation? -#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 16 }, - Package() { 0x0000ffff, 1, 0, 17 }, - Package() { 0x0000ffff, 2, 0, 18 }, - Package() { 0x0000ffff, 3, 0, 19 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 1, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 2, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 3, _SB.PCI0.LPCB.LNKD, 0 } - }) - - } - - } -} - -Device (RP02) -{ - NAME(_ADR, 0x001c0001) // FIXME: Have a macro for PCI Devices -> ACPI notation? -#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 17 }, - Package() { 0x0000ffff, 1, 0, 18 }, - Package() { 0x0000ffff, 2, 0, 19 }, - Package() { 0x0000ffff, 3, 0, 16 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 1, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 2, _SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 3, _SB.PCI0.LPCB.LNKA, 0 } - }) - - } - - } -} - - -Device (RP03) -{ - NAME(_ADR, 0x001c0002) // FIXME: Have a macro for PCI Devices -> ACPI notation? -#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 18 }, - Package() { 0x0000ffff, 1, 0, 19 }, - Package() { 0x0000ffff, 2, 0, 16 }, - Package() { 0x0000ffff, 3, 0, 17 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 1, _SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 2, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 3, _SB.PCI0.LPCB.LNKB, 0 } - }) - - } - - } -} - - -Device (RP04) -{ - NAME(_ADR, 0x001c0003) // FIXME: Have a macro for PCI Devices -> ACPI notation? -#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 19 }, - Package() { 0x0000ffff, 1, 0, 16 }, - Package() { 0x0000ffff, 2, 0, 17 }, - Package() { 0x0000ffff, 3, 0, 18 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, _SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 1, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 2, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 3, _SB.PCI0.LPCB.LNKC, 0 } - }) - - } - - } -} - - -Device (RP05) -{ - NAME(_ADR, 0x001c0004) // FIXME: Have a macro for PCI Devices -> ACPI notation? -#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 16 }, - Package() { 0x0000ffff, 1, 0, 17 }, - Package() { 0x0000ffff, 2, 0, 18 }, - Package() { 0x0000ffff, 3, 0, 19 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 1, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 2, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 3, _SB.PCI0.LPCB.LNKD, 0 } - }) - - } - - } -} - - -Device (RP06) -{ - NAME(_ADR, 0x001c0005) // FIXME: Have a macro for PCI Devices -> ACPI notation? -#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 17 }, - Package() { 0x0000ffff, 1, 0, 18 }, - Package() { 0x0000ffff, 2, 0, 19 }, - Package() { 0x0000ffff, 3, 0, 16 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 1, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 2, _SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 3, _SB.PCI0.LPCB.LNKA, 0 } - }) - - } - - } -} diff --git a/src/southbridge/intel/i82801jx/acpi/pcie_port.asl b/src/southbridge/intel/i82801jx/acpi/pcie_port.asl deleted file mode 100644 index 4e04ab2..0000000 --- a/src/southbridge/intel/i82801jx/acpi/pcie_port.asl +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The Chromium OS Authors. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Included in each PCIe Root Port device */ - -OperationRegion (RPCS, PCI_Config, 0x00, 0xFF) -Field (RPCS, AnyAcc, NoLock, Preserve) -{ - Offset (0x4c), // Link Capabilities - , 24, - RPPN, 8, // Root Port Number - Offset (0x5A), - , 3, - PDC, 1, - Offset (0xDF), - , 6, - HPCS, 1, -} diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index eaa2690..a25282a 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -81,7 +81,7 @@ #include "audio.asl"
// PCI Express Ports 0:1c.x -#include "pcie.asl" +#include <southbridge/intel/common/acpi/pcie.asl>
// USB 0:1d.0 and 0:1a.0 #include "usb.asl" diff --git a/src/southbridge/intel/lynxpoint/acpi/pcie.asl b/src/southbridge/intel/lynxpoint/acpi/pcie.asl deleted file mode 100644 index d7842cd..0000000 --- a/src/southbridge/intel/lynxpoint/acpi/pcie.asl +++ /dev/null @@ -1,213 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Intel 6/7 Series PCH PCIe support */ - -// PCI Express Ports - -Method (IRQM, 1, Serialized) { - - /* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */ - Name (IQAA, Package() { - Package() { 0x0000ffff, 0, 0, 16 }, - Package() { 0x0000ffff, 1, 0, 17 }, - Package() { 0x0000ffff, 2, 0, 18 }, - Package() { 0x0000ffff, 3, 0, 19 } }) - Name (IQAP, Package() { - Package() { 0x0000ffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 1, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 2, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 3, _SB.PCI0.LPCB.LNKD, 0 } }) - - /* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */ - Name (IQBA, Package() { - Package() { 0x0000ffff, 0, 0, 17 }, - Package() { 0x0000ffff, 1, 0, 18 }, - Package() { 0x0000ffff, 2, 0, 19 }, - Package() { 0x0000ffff, 3, 0, 16 } }) - Name (IQBP, Package() { - Package() { 0x0000ffff, 0, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 1, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 2, _SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 3, _SB.PCI0.LPCB.LNKA, 0 } }) - - /* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */ - Name (IQCA, Package() { - Package() { 0x0000ffff, 0, 0, 18 }, - Package() { 0x0000ffff, 1, 0, 19 }, - Package() { 0x0000ffff, 2, 0, 16 }, - Package() { 0x0000ffff, 3, 0, 17 } }) - Name (IQCP, Package() { - Package() { 0x0000ffff, 0, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 1, _SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 2, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 3, _SB.PCI0.LPCB.LNKB, 0 } }) - - /* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */ - Name (IQDA, Package() { - Package() { 0x0000ffff, 0, 0, 19 }, - Package() { 0x0000ffff, 1, 0, 16 }, - Package() { 0x0000ffff, 2, 0, 17 }, - Package() { 0x0000ffff, 3, 0, 18 } }) - Name (IQDP, Package() { - Package() { 0x0000ffff, 0, _SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 1, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 2, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 3, _SB.PCI0.LPCB.LNKC, 0 } }) - - Switch (ToInteger (Arg0)) { - /* PCIe Root Port 1 and 5 */ - Case (Package() { 1, 5 }) { - If (PICM) { - Return (IQAA) - } Else { - Return (IQAP) - } - } - - /* PCIe Root Port 2 and 6 */ - Case (Package() { 2, 6 }) { - If (PICM) { - Return (IQBA) - } Else { - Return (IQBP) - } - } - - /* PCIe Root Port 3 and 7 */ - Case (Package() { 3, 7 }) { - If (PICM) { - Return (IQCA) - } Else { - Return (IQCP) - } - } - - /* PCIe Root Port 4 and 8 */ - Case (Package() { 4, 8 }) { - If (PICM) { - Return (IQDA) - } Else { - Return (IQDP) - } - } - - Default { - If (PICM) { - Return (IQDA) - } Else { - Return (IQDP) - } - } - } -} - -Device (RP01) -{ - Name (_ADR, 0x001c0000) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP02) -{ - Name (_ADR, 0x001c0001) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP03) -{ - Name (_ADR, 0x001c0002) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP04) -{ - Name (_ADR, 0x001c0003) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP05) -{ - Name (_ADR, 0x001c0004) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP06) -{ - Name (_ADR, 0x001c0005) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP07) -{ - Name (_ADR, 0x001c0006) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP08) -{ - Name (_ADR, 0x001c0007) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} diff --git a/src/southbridge/intel/lynxpoint/acpi/pcie_port.asl b/src/southbridge/intel/lynxpoint/acpi/pcie_port.asl deleted file mode 100644 index 32ddead..0000000 --- a/src/southbridge/intel/lynxpoint/acpi/pcie_port.asl +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The Chromium OS Authors. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Included in each PCIe Root Port device */ - -OperationRegion (RPCS, PCI_Config, 0x00, 0xFF) -Field (RPCS, AnyAcc, NoLock, Preserve) -{ - Offset (0x4c), // Link Capabilities - , 24, - RPPN, 8, // Root Port Number -}
-
Arthur Heymans (Code Review)