Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44357 )
Change subject: soc/intel/xeon_sp/cpx: add CPUID for CPX-SP ES processor ......................................................................
soc/intel/xeon_sp/cpx: add CPUID for CPX-SP ES processor
Add CPUID for CPX-SP ES processor.
DeltaLake DVT server uses CPX-SP ES processor.
TESTED=booted DeltaLake DVT server to target OS. [root@localhost ~]# dmidecode -t 1 Getting SMBIOS data from sysfs. SMBIOS 3.0 present.
Handle 0x0001, DMI type 1, 27 bytes System Information Manufacturer: Wiwynn Product Name: Delta Lake DVT Version: YoDL03 Serial Number: BZA02200122N01A UUID: 000A0A22-2C29-1ED6-8259-000055DA2BFF Wake-up Type: Reserved SKU Number: Not Specified Family: DeltaLake
Signed-off-by: Jonathan Zhang jonzhang@fb.com Change-Id: Ic8975f6bf752fd685b38b2d1f0a4da41983b57f6 --- M src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/cpx/include/soc/cpu.h 2 files changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/44357/1
diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index cf903b8..f485b72 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -100,6 +100,7 @@
static const struct cpu_device_id cpu_table[] = { {X86_VENDOR_INTEL, CPUID_COOPERLAKE_SP_A0}, + {X86_VENDOR_INTEL, CPUID_COOPERLAKE_SP_ES}, {0, 0}, };
diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h index 1458000..e1c0171 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h @@ -7,6 +7,7 @@ #include <cpu/x86/msr.h>
#define CPUID_COOPERLAKE_SP_A0 0x05065a +#define CPUID_COOPERLAKE_SP_ES 0x05065b
/* CPU bus clock is fixed at 100MHz */ #define CPU_BCLK 100
Anjaneya "Reddy" Chagam has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44357 )
Change subject: soc/intel/xeon_sp/cpx: add CPUID for CPX-SP ES processor ......................................................................
Patch Set 1: Code-Review+1
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44357 )
Change subject: soc/intel/xeon_sp/cpx: add CPUID for CPX-SP ES processor ......................................................................
Patch Set 1: Code-Review+2
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44357 )
Change subject: soc/intel/xeon_sp/cpx: add CPUID for CPX-SP ES processor ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/44357/1/src/soc/intel/xeon_sp/cpx/i... File src/soc/intel/xeon_sp/cpx/include/soc/cpu.h:
https://review.coreboot.org/c/coreboot/+/44357/1/src/soc/intel/xeon_sp/cpx/i... PS1, Line 10: ES A1 See doc #621907
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44357 )
Change subject: soc/intel/xeon_sp/cpx: add CPUID for CPX-SP ES processor ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44357/1/src/soc/intel/xeon_sp/cpx/i... File src/soc/intel/xeon_sp/cpx/include/soc/cpu.h:
https://review.coreboot.org/c/coreboot/+/44357/1/src/soc/intel/xeon_sp/cpx/i... PS1, Line 10: ES
A1 […]
Thank you Maxim for solving this mystery. I had asked around, and was not able to figure out the answer. ;-) What is the title of doc #621907? I am not able to find it by ID.
Hello build bot (Jenkins), Anjaneya "Reddy" Chagam, Maxim Polyakov, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44357
to look at the new patch set (#2).
Change subject: soc/intel/xeon_sp/cpx: add CPUID for CPX-SP A1 processor ......................................................................
soc/intel/xeon_sp/cpx: add CPUID for CPX-SP A1 processor
Add CPUID for CPX-SP A1 (also called QS) processor.
DeltaLake DVT server uses CPX-SP A1 processor.
TESTED=booted DeltaLake DVT server to target OS. [root@localhost ~]# dmidecode -t 1 Getting SMBIOS data from sysfs. SMBIOS 3.0 present.
Handle 0x0001, DMI type 1, 27 bytes System Information Manufacturer: Wiwynn Product Name: Delta Lake DVT Version: YoDL03 Serial Number: BZA02200122N01A UUID: 000A0A22-2C29-1ED6-8259-000055DA2BFF Wake-up Type: Reserved SKU Number: Not Specified Family: DeltaLake
Signed-off-by: Jonathan Zhang jonzhang@fb.com Change-Id: Ic8975f6bf752fd685b38b2d1f0a4da41983b57f6 --- M src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/cpx/include/soc/cpu.h 2 files changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/44357/2
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44357 )
Change subject: soc/intel/xeon_sp/cpx: add CPUID for CPX-SP A1 processor ......................................................................
Patch Set 2: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/44357/1/src/soc/intel/xeon_sp/cpx/i... File src/soc/intel/xeon_sp/cpx/include/soc/cpu.h:
https://review.coreboot.org/c/coreboot/+/44357/1/src/soc/intel/xeon_sp/cpx/i... PS1, Line 10: ES
Thank you Maxim for solving this mystery. […]
You should log in into your Intel account as this information is confidential :) This is the "QU8R - Dear Customer Letter (DCL)" https://www.intel.com/content/www/us/en/search.html#q=621907&t=All A1 is the processor stepping, which is usually added to the name in these macros.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44357 )
Change subject: soc/intel/xeon_sp/cpx: add CPUID for CPX-SP A1 processor ......................................................................
Patch Set 2: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44357 )
Change subject: soc/intel/xeon_sp/cpx: add CPUID for CPX-SP A1 processor ......................................................................
Patch Set 2: Code-Review+1
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44357 )
Change subject: soc/intel/xeon_sp/cpx: add CPUID for CPX-SP A1 processor ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44357/1/src/soc/intel/xeon_sp/cpx/i... File src/soc/intel/xeon_sp/cpx/include/soc/cpu.h:
https://review.coreboot.org/c/coreboot/+/44357/1/src/soc/intel/xeon_sp/cpx/i... PS1, Line 10: ES
You should log in into your Intel account as this information is confidential :) […]
I tried again, the searchs by doc ID and name do not find it. I am glad you have access to this doc. ;-)
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44357 )
Change subject: soc/intel/xeon_sp/cpx: add CPUID for CPX-SP A1 processor ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44357/1/src/soc/intel/xeon_sp/cpx/i... File src/soc/intel/xeon_sp/cpx/include/soc/cpu.h:
https://review.coreboot.org/c/coreboot/+/44357/1/src/soc/intel/xeon_sp/cpx/i... PS1, Line 10: ES
I tried again, the searchs by doc ID and name do not find it. […]
I'm glad the company I work for has access to a lot of intel resources, with the exception of your fsp. If fb and intel release fsp, then I will try to port coreboot to our server platforms ;)
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44357 )
Change subject: soc/intel/xeon_sp/cpx: add CPUID for CPX-SP A1 processor ......................................................................
soc/intel/xeon_sp/cpx: add CPUID for CPX-SP A1 processor
Add CPUID for CPX-SP A1 (also called QS) processor.
DeltaLake DVT server uses CPX-SP A1 processor.
TESTED=booted DeltaLake DVT server to target OS. [root@localhost ~]# dmidecode -t 1 Getting SMBIOS data from sysfs. SMBIOS 3.0 present.
Handle 0x0001, DMI type 1, 27 bytes System Information Manufacturer: Wiwynn Product Name: Delta Lake DVT Version: YoDL03 Serial Number: BZA02200122N01A UUID: 000A0A22-2C29-1ED6-8259-000055DA2BFF Wake-up Type: Reserved SKU Number: Not Specified Family: DeltaLake
Signed-off-by: Jonathan Zhang jonzhang@fb.com Change-Id: Ic8975f6bf752fd685b38b2d1f0a4da41983b57f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44357 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Maxim Polyakov max.senia.poliak@gmail.com Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net --- M src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/cpx/include/soc/cpu.h 2 files changed, 2 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved Maxim Polyakov: Looks good to me, approved
diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index cf903b8..db9dd4b 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -100,6 +100,7 @@
static const struct cpu_device_id cpu_table[] = { {X86_VENDOR_INTEL, CPUID_COOPERLAKE_SP_A0}, + {X86_VENDOR_INTEL, CPUID_COOPERLAKE_SP_A1}, {0, 0}, };
diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h index 1458000..3e74064 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h @@ -7,6 +7,7 @@ #include <cpu/x86/msr.h>
#define CPUID_COOPERLAKE_SP_A0 0x05065a +#define CPUID_COOPERLAKE_SP_A1 0x05065b
/* CPU bus clock is fixed at 100MHz */ #define CPU_BCLK 100
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Angel Pons (Code Review) -
Anjaneya "Reddy" Chagam (Code Review)
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Jonathan Zhang (Code Review)
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Maxim Polyakov (Code Review)
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Paul Menzel (Code Review)