Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35736 )
Change subject: [WIP] soc/intel: Refactor device ACPI names ......................................................................
[WIP] soc/intel: Refactor device ACPI names
Change-Id: I0f2ee991efbd0911dfce5fdf5c5d92de9b7cc652 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/soc/intel/apollolake/chip.c M src/soc/intel/cannonlake/chip.c M src/soc/intel/fsp_broadwell_de/southcluster.c M src/soc/intel/icelake/chip.c M src/soc/intel/skylake/acpi.c 5 files changed, 21 insertions(+), 237 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/35736/1
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 8e516f8..e53bb0c 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -147,65 +147,10 @@ if (dev->path.type != DEVICE_PATH_PCI) return NULL;
- switch (dev->path.pci.devfn) { - /* DSDT: acpi/northbridge.asl */ - case SA_DEVFN_ROOT: - return "MCHC"; - /* DSDT: acpi/lpc.asl */ - case PCH_DEVFN_LPC: - return "LPCB"; - /* DSDT: acpi/xhci.asl */ - case PCH_DEVFN_XHCI: - return "XHCI"; - /* DSDT: acpi/pch_hda.asl */ - case PCH_DEVFN_HDA: - return "HDAS"; - /* DSDT: acpi/lpss.asl */ - case PCH_DEVFN_UART0: - return "URT1"; - case PCH_DEVFN_UART1: - return "URT2"; - case PCH_DEVFN_UART2: - return "URT3"; - case PCH_DEVFN_UART3: - return "URT4"; - case PCH_DEVFN_SPI0: - return "SPI1"; - case PCH_DEVFN_SPI1: - return "SPI2"; - case PCH_DEVFN_SPI2: - return "SPI3"; - case PCH_DEVFN_PWM: - return "PWM"; - case PCH_DEVFN_I2C0: - return "I2C0"; - case PCH_DEVFN_I2C1: - return "I2C1"; - case PCH_DEVFN_I2C2: - return "I2C2"; - case PCH_DEVFN_I2C3: - return "I2C3"; - case PCH_DEVFN_I2C4: - return "I2C4"; - case PCH_DEVFN_I2C5: - return "I2C5"; - case PCH_DEVFN_I2C6: - return "I2C6"; - case PCH_DEVFN_I2C7: - return "I2C7"; - /* Storage */ - case PCH_DEVFN_SDCARD: - return "SDCD"; - case PCH_DEVFN_EMMC: - return "EMMC"; - case PCH_DEVFN_SDIO: - return "SDIO"; - /* PCIe */ - case PCH_DEVFN_PCIE1: - return "RP03"; - case PCH_DEVFN_PCIE5: - return "RP01"; - } +#if 0 + /* FIXME dev->acpi_name */ + return dev->acpi_name; +#endif
return NULL; } diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 0ce2f1a..1754964 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -74,66 +74,10 @@ if (dev->path.type != DEVICE_PATH_PCI) return NULL;
- switch (dev->path.pci.devfn) { - case SA_DEVFN_ROOT: return "MCHC"; - case SA_DEVFN_IGD: return "GFX0"; - case PCH_DEVFN_ISH: return "ISHB"; - case PCH_DEVFN_XHCI: return "XHCI"; - case PCH_DEVFN_USBOTG: return "XDCI"; - case PCH_DEVFN_THERMAL: return "THRM"; - case PCH_DEVFN_I2C0: return "I2C0"; - case PCH_DEVFN_I2C1: return "I2C1"; - case PCH_DEVFN_I2C2: return "I2C2"; - case PCH_DEVFN_I2C3: return "I2C3"; - case PCH_DEVFN_CSE: return "CSE1"; - case PCH_DEVFN_CSE_2: return "CSE2"; - case PCH_DEVFN_CSE_IDER: return "CSED"; - case PCH_DEVFN_CSE_KT: return "CSKT"; - case PCH_DEVFN_CSE_3: return "CSE3"; - case PCH_DEVFN_SATA: return "SATA"; - case PCH_DEVFN_UART2: return "UAR2"; - case PCH_DEVFN_I2C4: return "I2C4"; - case PCH_DEVFN_I2C5: return "I2C5"; - case PCH_DEVFN_PCIE1: return "RP01"; - case PCH_DEVFN_PCIE2: return "RP02"; - case PCH_DEVFN_PCIE3: return "RP03"; - case PCH_DEVFN_PCIE4: return "RP04"; - case PCH_DEVFN_PCIE5: return "RP05"; - case PCH_DEVFN_PCIE6: return "RP06"; - case PCH_DEVFN_PCIE7: return "RP07"; - case PCH_DEVFN_PCIE8: return "RP08"; - case PCH_DEVFN_PCIE9: return "RP09"; - case PCH_DEVFN_PCIE10: return "RP10"; - case PCH_DEVFN_PCIE11: return "RP11"; - case PCH_DEVFN_PCIE12: return "RP12"; - case PCH_DEVFN_PCIE13: return "RP13"; - case PCH_DEVFN_PCIE14: return "RP14"; - case PCH_DEVFN_PCIE15: return "RP15"; - case PCH_DEVFN_PCIE16: return "RP16"; - case PCH_DEVFN_PCIE17: return "RP17"; - case PCH_DEVFN_PCIE18: return "RP18"; - case PCH_DEVFN_PCIE19: return "RP19"; - case PCH_DEVFN_PCIE20: return "RP20"; - case PCH_DEVFN_PCIE21: return "RP21"; - case PCH_DEVFN_PCIE22: return "RP22"; - case PCH_DEVFN_PCIE23: return "RP23"; - case PCH_DEVFN_PCIE24: return "RP24"; - case PCH_DEVFN_UART0: return "UAR0"; - case PCH_DEVFN_UART1: return "UAR1"; - case PCH_DEVFN_GSPI0: return "SPI0"; - case PCH_DEVFN_GSPI1: return "SPI1"; - case PCH_DEVFN_GSPI2: return "SPI2"; - case PCH_DEVFN_EMMC: return "EMMC"; - case PCH_DEVFN_SDCARD: return "SDXC"; - case PCH_DEVFN_LPC: return "LPCB"; - case PCH_DEVFN_P2SB: return "P2SB"; - case PCH_DEVFN_PMC: return "PMC_"; - case PCH_DEVFN_HDA: return "HDAS"; - case PCH_DEVFN_SMBUS: return "SBUS"; - case PCH_DEVFN_SPI: return "FSPI"; - case PCH_DEVFN_GBE: return "IGBE"; - case PCH_DEVFN_TRACEHUB:return "THUB"; - } +#if 0 + /* FIXME dev->acpi_name */ + return dev->acpi_name; +#endif
return NULL; } diff --git a/src/soc/intel/fsp_broadwell_de/southcluster.c b/src/soc/intel/fsp_broadwell_de/southcluster.c index 31dcc25..2ad5f52 100644 --- a/src/soc/intel/fsp_broadwell_de/southcluster.c +++ b/src/soc/intel/fsp_broadwell_de/southcluster.c @@ -280,10 +280,11 @@ #if CONFIG(HAVE_ACPI_TABLES) static const char *lpc_acpi_name(const struct device *dev) { - if (dev->path.pci.devfn == PCH_DEVFN_LPC) - return "LPC0"; - else - return NULL; +#if 0 + /* FIXME dev->acpi_name */ + return dev->acpi_name; +#endif + return NULL; } #endif
diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c index 2bb908c..956f35f 100644 --- a/src/soc/intel/icelake/chip.c +++ b/src/soc/intel/icelake/chip.c @@ -37,67 +37,10 @@ if (dev->path.type != DEVICE_PATH_PCI) return NULL;
- switch (dev->path.pci.devfn) { - case SA_DEVFN_ROOT: return "MCHC"; - case SA_DEVFN_IGD: return "GFX0"; - case PCH_DEVFN_ISH: return "ISHB"; - case PCH_DEVFN_XHCI: return "XHCI"; - case PCH_DEVFN_USBOTG: return "XDCI"; - case PCH_DEVFN_THERMAL: return "THRM"; - case PCH_DEVFN_I2C0: return "I2C0"; - case PCH_DEVFN_I2C1: return "I2C1"; - case PCH_DEVFN_I2C2: return "I2C2"; - case PCH_DEVFN_I2C3: return "I2C3"; - case PCH_DEVFN_CSE: return "CSE1"; - case PCH_DEVFN_CSE_2: return "CSE2"; - case PCH_DEVFN_CSE_IDER: return "CSED"; - case PCH_DEVFN_CSE_KT: return "CSKT"; - case PCH_DEVFN_CSE_3: return "CSE3"; - case PCH_DEVFN_SATA: return "SATA"; - case PCH_DEVFN_UART2: return "UAR2"; - case PCH_DEVFN_I2C4: return "I2C4"; - case PCH_DEVFN_I2C5: return "I2C5"; - case PCH_DEVFN_PCIE1: return "RP01"; - case PCH_DEVFN_PCIE2: return "RP02"; - case PCH_DEVFN_PCIE3: return "RP03"; - case PCH_DEVFN_PCIE4: return "RP04"; - case PCH_DEVFN_PCIE5: return "RP05"; - case PCH_DEVFN_PCIE6: return "RP06"; - case PCH_DEVFN_PCIE7: return "RP07"; - case PCH_DEVFN_PCIE8: return "RP08"; - case PCH_DEVFN_PCIE9: return "RP09"; - case PCH_DEVFN_PCIE10: return "RP10"; - case PCH_DEVFN_PCIE11: return "RP11"; - case PCH_DEVFN_PCIE12: return "RP12"; - case PCH_DEVFN_PCIE13: return "RP13"; - case PCH_DEVFN_PCIE14: return "RP14"; - case PCH_DEVFN_PCIE15: return "RP15"; - case PCH_DEVFN_PCIE16: return "RP16"; - case PCH_DEVFN_PCIE17: return "RP17"; - case PCH_DEVFN_PCIE18: return "RP18"; - case PCH_DEVFN_PCIE19: return "RP19"; - case PCH_DEVFN_PCIE20: return "RP20"; - case PCH_DEVFN_PCIE21: return "RP21"; - case PCH_DEVFN_PCIE22: return "RP22"; - case PCH_DEVFN_PCIE23: return "RP23"; - case PCH_DEVFN_PCIE24: return "RP24"; - case PCH_DEVFN_UART0: return "UAR0"; - case PCH_DEVFN_UART1: return "UAR1"; - case PCH_DEVFN_GSPI0: return "SPI0"; - case PCH_DEVFN_GSPI1: return "SPI1"; - case PCH_DEVFN_GSPI2: return "SPI2"; - case PCH_DEVFN_EMMC: return "EMMC"; - case PCH_DEVFN_SDCARD: return "SDXC"; - /* Keeping ACPI device name coherent with ec.asl */ - case PCH_DEVFN_ESPI: return "LPCB"; - case PCH_DEVFN_P2SB: return "P2SB"; - case PCH_DEVFN_PMC: return "PMC_"; - case PCH_DEVFN_HDA: return "HDAS"; - case PCH_DEVFN_SMBUS: return "SBUS"; - case PCH_DEVFN_SPI: return "FSPI"; - case PCH_DEVFN_GBE: return "IGBE"; - case PCH_DEVFN_TRACEHUB:return "THUB"; - } +#if 0 + /* FIXME dev->acpi_name */ + return dev->acpi_name; +#endif
return NULL; } diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 43f9c39..45756b3 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -760,59 +760,10 @@ if (dev->path.type != DEVICE_PATH_PCI) return NULL;
- switch (dev->path.pci.devfn) { - case SA_DEVFN_ROOT: return "MCHC"; - case SA_DEVFN_IGD: return "GFX0"; - case PCH_DEVFN_ISH: return "ISHB"; - case PCH_DEVFN_XHCI: return "XHCI"; - case PCH_DEVFN_USBOTG: return "XDCI"; - case PCH_DEVFN_THERMAL: return "THRM"; - case PCH_DEVFN_CIO: return "ICIO"; - case PCH_DEVFN_I2C0: return "I2C0"; - case PCH_DEVFN_I2C1: return "I2C1"; - case PCH_DEVFN_I2C2: return "I2C2"; - case PCH_DEVFN_I2C3: return "I2C3"; - case PCH_DEVFN_CSE: return "CSE1"; - case PCH_DEVFN_CSE_2: return "CSE2"; - case PCH_DEVFN_CSE_IDER: return "CSED"; - case PCH_DEVFN_CSE_KT: return "CSKT"; - case PCH_DEVFN_CSE_3: return "CSE3"; - case PCH_DEVFN_SATA: return "SATA"; - case PCH_DEVFN_UART2: return "UAR2"; - case PCH_DEVFN_I2C4: return "I2C4"; - case PCH_DEVFN_I2C5: return "I2C5"; - case PCH_DEVFN_PCIE1: return "RP01"; - case PCH_DEVFN_PCIE2: return "RP02"; - case PCH_DEVFN_PCIE3: return "RP03"; - case PCH_DEVFN_PCIE4: return "RP04"; - case PCH_DEVFN_PCIE5: return "RP05"; - case PCH_DEVFN_PCIE6: return "RP06"; - case PCH_DEVFN_PCIE7: return "RP07"; - case PCH_DEVFN_PCIE8: return "RP08"; - case PCH_DEVFN_PCIE9: return "RP09"; - case PCH_DEVFN_PCIE10: return "RP10"; - case PCH_DEVFN_PCIE11: return "RP11"; - case PCH_DEVFN_PCIE12: return "RP12"; - case PCH_DEVFN_PCIE13: return "RP13"; - case PCH_DEVFN_PCIE14: return "RP14"; - case PCH_DEVFN_PCIE15: return "RP15"; - case PCH_DEVFN_PCIE16: return "RP16"; - case PCH_DEVFN_UART0: return "UAR0"; - case PCH_DEVFN_UART1: return "UAR1"; - case PCH_DEVFN_GSPI0: return "SPI0"; - case PCH_DEVFN_GSPI1: return "SPI1"; - case PCH_DEVFN_EMMC: return "EMMC"; - case PCH_DEVFN_SDIO: return "SDIO"; - case PCH_DEVFN_SDCARD: return "SDXC"; - case PCH_DEVFN_LPC: return "LPCB"; - case PCH_DEVFN_P2SB: return "P2SB"; - case PCH_DEVFN_PMC: return "PMC_"; - case PCH_DEVFN_HDA: return "HDAS"; - case PCH_DEVFN_SMBUS: return "SBUS"; - case PCH_DEVFN_SPI: return "FSPI"; - case PCH_DEVFN_GBE: return "IGBE"; - case PCH_DEVFN_TRACEHUB:return "THUB"; - } +#if 0 + /* FIXME dev->acpi_name */ + return dev->acpi_name; +#endif
return NULL; }
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35736 )
Change subject: [WIP] soc/intel: Refactor device ACPI names ......................................................................
Patch Set 1:
I think we would want to push these strings to devicetree.cb.
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35736 )
Change subject: [WIP] soc/intel: Refactor device ACPI names ......................................................................
Patch Set 1:
Presumably this includes a way through sconfig of supplying an ACPI name to hang off the struct device?
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35736 )
Change subject: [WIP] soc/intel: Refactor device ACPI names ......................................................................
Patch Set 3:
Patch Set 1:
I think we would want to push these strings to devicetree.cb.
Devicetree does not seem appropriate as this is an SOC level binding and not something the mainboard should tweak. These names need to match what is in any static ASL.
Hello Aaron Durbin, Patrick Rudolph, Duncan Laurie, Philipp Deppenwiese, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35736
to look at the new patch set (#4).
Change subject: [WIP] soc/intel: Refactor device ACPI names ......................................................................
[WIP] soc/intel: Refactor device ACPI names
Change-Id: I0f2ee991efbd0911dfce5fdf5c5d92de9b7cc652 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/soc/intel/apollolake/chip.c M src/soc/intel/cannonlake/chip.c M src/soc/intel/fsp_broadwell_de/southcluster.c M src/soc/intel/icelake/chip.c M src/soc/intel/skylake/acpi.c 5 files changed, 21 insertions(+), 237 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/35736/4
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35736 )
Change subject: [WIP] soc/intel: Refactor device ACPI names ......................................................................
Patch Set 4:
Patch Set 3:
Patch Set 1:
I think we would want to push these strings to devicetree.cb.
Devicetree does not seem appropriate as this is an SOC level binding and not something the mainboard should tweak. These names need to match what is in any static ASL.
Static ASL already has to match strings in soc/*.c. https://review.coreboot.org/c/coreboot/+/35734/2/src/soc/intel/fsp_broadwell...
I agree these identifiers should not be defined in mb/x/devicetree.cb, but we may be introducing soc/x/devicetree.cb files to define alias names for PCI functions.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35736 )
Change subject: [WIP] soc/intel: Refactor device ACPI names ......................................................................
Patch Set 7: Code-Review+1
Kyösti Mälkki has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/35736 )
Change subject: [WIP] soc/intel: Refactor device ACPI names ......................................................................
Abandoned
-
Aaron Durbin (Code Review) -
Angel Pons (Code Review)
-
Duncan Laurie (Code Review)
-
Kyösti Mälkki (Code Review)