Change in coreboot[master]: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating

[Subrata Banik (Code Review)]

Attention is currently required from: Tim Wawrzynczak, Sridhar Siricilla, Kane Chen.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63293 )

Change subject: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating
......................................................................

Patch Set 2:

(1 comment)

Patchset:

PS2: 
I believe we need to default disable USB2 PHY power gating for all ADL-P devices irrespective of internal or external VRs in HW design.

Just don't wish to leave with this issue unknowingly for other ADL design.

@Paul, refer to Intel doc 723158 for the detailed reasoning. I believe it also requires the commitmsg update.