Attention is currently required from: Tim Wawrzynczak, Sridhar Siricilla, Kane Chen.

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1 comment:

• Patchset:

  • Patch Set #2:

    I believe we need to default disable USB2 PHY power gating for all ADL-P devices irrespective of internal or external VRs in HW design.

    Just don't wish to leave with this issue unknowingly for other ADL design.

    @Paul, refer to Intel doc 723158 for the detailed reasoning. I believe it also requires the commitmsg update.

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