Change in coreboot[master]: soc/intel/skl: set PEG port state to auto

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48304 )

Change subject: soc/intel/skl: set PEG port state to auto
......................................................................

soc/intel/skl: set PEG port state to auto

Setting PegXEnable to 1, statically enables the PEG ports, which blocks
the SoC from going to deeper PC states. Instead, set the state to "auto"
(2), so the port gets disabled, when no device was detected.

Note: Currently, this only works with the AST PCI bridge disabled or the
      VGA jumper set to disabled on coreboot, while it works on vendor
      in any case. The reason for this is still unclear.

Test: powertop on X11SSM-F shows SoC in PC8 like on vendor firmware
      instead of just PC3

Signed-off-by: Michael Niewöhner 
Change-Id: I3933a219b77d7234af273217df031cf627b4071f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48304
Tested-by: build bot (Jenkins) 
Reviewed-by:  Felix Singer 
Reviewed-by: Paul Menzel 
Reviewed-by: Furquan Shaikh 
---
M src/soc/intel/skylake/romstage/romstage.c
1 file changed, 3 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Paul Menzel: Looks good to me, but someone else must approve
  Furquan Shaikh: Looks good to me, approved
   Felix Singer: Looks good to me, approved

diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 5e0d687..a7ce2f8 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -173,6 +173,7 @@
    dev = pcidev_path_on_root(SA_DEVFN_PEG0); /* PEG 0:1:0 */
    m_cfg->Peg0Enable = dev && dev->enabled;
    if (m_cfg->Peg0Enable) {
+		m_cfg->Peg0Enable = 2;
    	m_cfg->Peg0MaxLinkWidth = config->Peg0MaxLinkWidth;
    	/* Use maximum possible link speed */
    	m_cfg->Peg0MaxLinkSpeed = 0;
@@ -186,6 +187,7 @@
    dev = pcidev_path_on_root(SA_DEVFN_PEG1); /* PEG 0:1:1 */
    m_cfg->Peg1Enable = dev && dev->enabled;
    if (m_cfg->Peg1Enable) {
+		m_cfg->Peg1Enable = 2;
    	m_cfg->Peg1MaxLinkWidth = config->Peg1MaxLinkWidth;
    	m_cfg->Peg1MaxLinkSpeed = 0;
    	m_cfg->Peg1PowerDownUnusedLanes = 1;
@@ -196,6 +198,7 @@
    dev = pcidev_path_on_root(SA_DEVFN_PEG2); /* PEG 0:1:2 */
    m_cfg->Peg2Enable = dev && dev->enabled;
    if (m_cfg->Peg2Enable) {
+		m_cfg->Peg2Enable = 2;
    	m_cfg->Peg2MaxLinkWidth = config->Peg2MaxLinkWidth;
    	m_cfg->Peg2MaxLinkSpeed = 0;
    	m_cfg->Peg2PowerDownUnusedLanes = 1;