Patrick Georgi submitted this change.

View Change

Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Furquan Shaikh: Looks good to me, approved Felix Singer: Looks good to me, approved
soc/intel/skl: set PEG port state to auto

Setting PegXEnable to 1, statically enables the PEG ports, which blocks
the SoC from going to deeper PC states. Instead, set the state to "auto"
(2), so the port gets disabled, when no device was detected.

Note: Currently, this only works with the AST PCI bridge disabled or the
VGA jumper set to disabled on coreboot, while it works on vendor
in any case. The reason for this is still unclear.

Test: powertop on X11SSM-F shows SoC in PC8 like on vendor firmware
instead of just PC3

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I3933a219b77d7234af273217df031cf627b4071f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
---
M src/soc/intel/skylake/romstage/romstage.c
1 file changed, 3 insertions(+), 0 deletions(-)

diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 5e0d687..a7ce2f8 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -173,6 +173,7 @@
dev = pcidev_path_on_root(SA_DEVFN_PEG0); /* PEG 0:1:0 */
m_cfg->Peg0Enable = dev && dev->enabled;
if (m_cfg->Peg0Enable) {
+ m_cfg->Peg0Enable = 2;
m_cfg->Peg0MaxLinkWidth = config->Peg0MaxLinkWidth;
/* Use maximum possible link speed */
m_cfg->Peg0MaxLinkSpeed = 0;
@@ -186,6 +187,7 @@
dev = pcidev_path_on_root(SA_DEVFN_PEG1); /* PEG 0:1:1 */
m_cfg->Peg1Enable = dev && dev->enabled;
if (m_cfg->Peg1Enable) {
+ m_cfg->Peg1Enable = 2;
m_cfg->Peg1MaxLinkWidth = config->Peg1MaxLinkWidth;
m_cfg->Peg1MaxLinkSpeed = 0;
m_cfg->Peg1PowerDownUnusedLanes = 1;
@@ -196,6 +198,7 @@
dev = pcidev_path_on_root(SA_DEVFN_PEG2); /* PEG 0:1:2 */
m_cfg->Peg2Enable = dev && dev->enabled;
if (m_cfg->Peg2Enable) {
+ m_cfg->Peg2Enable = 2;
m_cfg->Peg2MaxLinkWidth = config->Peg2MaxLinkWidth;
m_cfg->Peg2MaxLinkSpeed = 0;
m_cfg->Peg2PowerDownUnusedLanes = 1;

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I3933a219b77d7234af273217df031cf627b4071f
Gerrit-Change-Number: 48304
Gerrit-PatchSet: 6
Gerrit-Owner: Michael Niewöhner <foss@mniewoehner.de>
Gerrit-Reviewer: Felix Singer <felixsinger@posteo.net>
Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com>
Gerrit-Reviewer: Furquan Shaikh <furquan@google.com>
Gerrit-Reviewer: Nico Huber <nico.h@gmx.de>
Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com>
Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org>
Gerrit-Reviewer: Paul Menzel <paulepanter@users.sourceforge.net>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak@chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-MessageType: merged