Change in coreboot[master]: mb/purism/librem_mini: Update smbios_slot_desc for M.2/WLAN

[Matt DeVillier (Code Review)]

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47251 )

Change subject: mb/purism/librem_mini: Update smbios_slot_desc for M.2/WLAN
......................................................................

mb/purism/librem_mini: Update smbios_slot_desc for M.2/WLAN

Add strings for M.2 keying and number of PCIe lanes.

Change-Id: I2e13749b50263ee5c2388a419bc8d784af6bd880
Signed-off-by: Matt DeVillier 
---
M src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/47251/1

diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb
index e02586c..1a1c466 100644
--- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb
+++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb
@@ -197,7 +197,7 @@
    		register "PcieRpLtrEnable[7]" = "1"
    		# ClkSrcUsage must be set to free-run since SRCCLKREQ2 is NC
    		register "PcieClkSrcUsage[2]" = "0x80"
-			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther"
+			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (WLAN)" "SlotDataBusWidth1X"
    	end
    	device pci 1d.0 off end # PCI Express Port 9
    	device pci 1d.1 on	# PCI Express Port 10

[Matt DeVillier (Code Review)]

Hello build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/47251

to look at the new patch set (#2).

Change subject: mb/purism/librem_mini: Update smbios_slot_desc for M.2/WLAN
......................................................................

mb/purism/librem_mini: Update smbios_slot_desc for M.2/WLAN

Add strings for M.2 keying and number of PCIe lanes.

Change-Id: I2e13749b50263ee5c2388a419bc8d784af6bd880
Signed-off-by: Matt DeVillier 
---
M src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/47251/2

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47251 )

Change subject: mb/purism/librem_mini: Update smbios_slot_desc for M.2/WLAN
......................................................................

Patch Set 2: Code-Review+2

[Michael Niewöhner (Code Review)]

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47251 )

Change subject: mb/purism/librem_mini: Update smbios_slot_desc for M.2/WLAN
......................................................................

Patch Set 2: Code-Review+2

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47251 )

Change subject: mb/purism/librem_mini: Update smbios_slot_desc for M.2/WLAN
......................................................................

mb/purism/librem_mini: Update smbios_slot_desc for M.2/WLAN

Add strings for M.2 keying and number of PCIe lanes.

Change-Id: I2e13749b50263ee5c2388a419bc8d784af6bd880
Signed-off-by: Matt DeVillier 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47251
Reviewed-by: Angel Pons 
Reviewed-by: Michael Niewöhner 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved
  Michael Niewöhner: Looks good to me, approved

diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb
index becb946..e2135b7 100644
--- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb
+++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb
@@ -197,7 +197,7 @@
    		register "PcieRpLtrEnable[7]" = "1"
    		# ClkSrcUsage must be set to free-run since SRCCLKREQ2 is NC
    		register "PcieClkSrcUsage[2]" = "0x80"
-			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther"
+			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X"
    	end
    	device pci 1d.0 off end # PCI Express Port 9
    	device pci 1d.1 on	# PCI Express Port 10