Patrick Georgi submitted this change.

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Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Michael Niewöhner: Looks good to me, approved
mb/purism/librem_mini: Update smbios_slot_desc for M.2/WLAN

Add strings for M.2 keying and number of PCIe lanes.

Change-Id: I2e13749b50263ee5c2388a419bc8d784af6bd880
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47251
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
M src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb
index becb946..e2135b7 100644
--- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb
+++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb
@@ -197,7 +197,7 @@
register "PcieRpLtrEnable[7]" = "1"
# ClkSrcUsage must be set to free-run since SRCCLKREQ2 is NC
register "PcieClkSrcUsage[2]" = "0x80"
- smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther"
+ smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X"
end
device pci 1d.0 off end # PCI Express Port 9
device pci 1d.1 on # PCI Express Port 10

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I2e13749b50263ee5c2388a419bc8d784af6bd880
Gerrit-Change-Number: 47251
Gerrit-PatchSet: 4
Gerrit-Owner: Matt DeVillier <matt.devillier@gmail.com>
Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com>
Gerrit-Reviewer: Michael Niewöhner <foss@mniewoehner.de>
Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net>
Gerrit-MessageType: merged