HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32700
Change subject: sb/bd82x6x: Don't rewrite over BCTRL ......................................................................
sb/bd82x6x: Don't rewrite over BCTRL
PCI_MIN_GNT doesn't exist for PCI bridges. PCI_MIN_GNT is defined at 0x3e, and at that offset, we have BCTRL register. Some lines obove that code line, the "write" on BCTRL is already done.
Change-Id: I8f1b98ba627947ab6652a4ba31d2acb159dd3e32 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/southbridge/intel/bd82x6x/pci.c 1 file changed, 0 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/32700/1
diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c index c3b8257..2186287 100644 --- a/src/southbridge/intel/bd82x6x/pci.c +++ b/src/southbridge/intel/bd82x6x/pci.c @@ -47,9 +47,6 @@ reg8 |= (0x04 << 3); pci_write_config8(dev, SMLT, reg8);
- /* Will this improve throughput of bus masters? */ - pci_write_config8(dev, PCI_MIN_GNT, 0x06); - /* Clear errors in status registers */ reg16 = pci_read_config16(dev, PSTS); //reg16 |= 0xf900;
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32700
to look at the new patch set (#2).
Change subject: sb/bd82x6x: Don't rewrite over BCTRL ......................................................................
sb/bd82x6x: Don't rewrite over BCTRL
PCI_MIN_GNT is defined at offset 0x3e in <pci_def.h> which does not apply to this PCI bridge because it is only defined for "Header type 0 (normal devices)" (line 82). Some lines obove that code line, the "write" on BCTRL is already done.
Change-Id: I8f1b98ba627947ab6652a4ba31d2acb159dd3e32 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/southbridge/intel/bd82x6x/pci.c 1 file changed, 0 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/32700/2
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32700 )
Change subject: sb/bd82x6x: Don't rewrite over BCTRL ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32700 )
Change subject: sb/bd82x6x: Don't rewrite over BCTRL ......................................................................
sb/bd82x6x: Don't rewrite over BCTRL
PCI_MIN_GNT is defined at offset 0x3e in <pci_def.h> which does not apply to this PCI bridge because it is only defined for "Header type 0 (normal devices)" (line 82). Some lines obove that code line, the "write" on BCTRL is already done.
Change-Id: I8f1b98ba627947ab6652a4ba31d2acb159dd3e32 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/32700 Reviewed-by: Nico Huber nico.h@gmx.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/southbridge/intel/bd82x6x/pci.c 1 file changed, 0 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c index c3b8257..2186287 100644 --- a/src/southbridge/intel/bd82x6x/pci.c +++ b/src/southbridge/intel/bd82x6x/pci.c @@ -47,9 +47,6 @@ reg8 |= (0x04 << 3); pci_write_config8(dev, SMLT, reg8);
- /* Will this improve throughput of bus masters? */ - pci_write_config8(dev, PCI_MIN_GNT, 0x06); - /* Clear errors in status registers */ reg16 = pci_read_config16(dev, PSTS); //reg16 |= 0xf900;
-
HAOUAS Elyes (Code Review) -
Nico Huber (Code Review)
-
Patrick Georgi (Code Review)