HAOUAS Elyes uploaded patch set #2 to this change.

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sb/bd82x6x: Don't rewrite over BCTRL

PCI_MIN_GNT is defined at offset 0x3e in <pci_def.h> which does not
apply to this PCI bridge because it is only defined for
"Header type 0 (normal devices)" (line 82).
Some lines obove that code line, the "write" on BCTRL is already done.

Change-Id: I8f1b98ba627947ab6652a4ba31d2acb159dd3e32
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
---
M src/southbridge/intel/bd82x6x/pci.c
1 file changed, 0 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/32700/2

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I8f1b98ba627947ab6652a4ba31d2acb159dd3e32
Gerrit-Change-Number: 32700
Gerrit-PatchSet: 2
Gerrit-Owner: HAOUAS Elyes <ehaouas@noos.fr>
Gerrit-Reviewer: HAOUAS Elyes <ehaouas@noos.fr>
Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-MessageType: newpatchset