Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48488 )
Change subject: soc/amd/cezanne: add 0xcf9 reset ......................................................................
soc/amd/cezanne: add 0xcf9 reset
This also temporary adds a prototype for chipset_handle_reset that will be removed when the FSP integration gets added.
Change-Id: Ibb78661c102e0d0327f3e74173bf98bc40e13960 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/mainboard/amd/majolica/Kconfig M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/cezanne/include/soc/iomap.h A src/soc/amd/cezanne/include/soc/reset.h M src/soc/amd/cezanne/include/soc/southbridge.h A src/soc/amd/cezanne/reset.c 7 files changed, 82 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/48488/1
diff --git a/src/mainboard/amd/majolica/Kconfig b/src/mainboard/amd/majolica/Kconfig index f811c39..cb3237c 100644 --- a/src/mainboard/amd/majolica/Kconfig +++ b/src/mainboard/amd/majolica/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select SOC_AMD_CEZANNE - select MISSING_BOARD_RESET
config FMDFILE string diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index aec9a47..894d8e7 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -13,6 +13,7 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 + select HAVE_CF9_RESET select IOAPIC select RESET_VECTOR_IN_RAM select SOC_AMD_COMMON diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 946e480..15db2e6 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -6,10 +6,15 @@
bootblock-y += bootblock.c bootblock-y += early_fch.c +bootblock-y += reset.c
+verstage_x86-y += reset.c + +romstage-y += reset.c romstage-y += romstage.c
ramstage-y += chip.c +ramstage-y += reset.c
CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include
diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h index 96313ea..4d47f7e 100644 --- a/src/soc/amd/cezanne/include/soc/iomap.h +++ b/src/soc/amd/cezanne/include/soc/iomap.h @@ -4,6 +4,7 @@ #define AMD_CEZANNE_IOMAP_H
/* I/O Ranges */ -#define SMB_BASE_ADDR 0xb00 +#define NCP_ERR 0x00f0 +#define SMB_BASE_ADDR 0x0b00
#endif /* AMD_CEZANNE_IOMAP_H */ diff --git a/src/soc/amd/cezanne/include/soc/reset.h b/src/soc/amd/cezanne/include/soc/reset.h new file mode 100644 index 0000000..89dd63e --- /dev/null +++ b/src/soc/amd/cezanne/include/soc/reset.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_CEZANNE_RESET_H +#define AMD_CEZANNE_RESET_H + +void set_warm_reset_flag(void); +int is_warm_reset(void); + +/* TODO: remove when <fsp/util.h> gets added back */ +void chipset_handle_reset(uint32_t status); + +#endif /* AMD_CEZANNE_RESET_H */ diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index 2456ebc..03ee2bb 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -5,6 +5,13 @@
#include <soc/iomap.h>
+/* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */ +#define PWR_RESET_CFG 0x10 +#define TOGGLE_ALL_PWR_GOOD (1 << 1) + +/* IO 0xf0 NCP Error */ +#define NCP_WARM_BOOT (1 << 7) /* Write-once */ + void fch_pre_init(void); void fch_early_init(void);
diff --git a/src/soc/amd/cezanne/reset.c b/src/soc/amd/cezanne/reset.c new file mode 100644 index 0000000..ea2c93f --- /dev/null +++ b/src/soc/amd/cezanne/reset.c @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/io.h> +#include <console/console.h> +#include <cf9_reset.h> +#include <reset.h> +#include <soc/reset.h> +#include <soc/southbridge.h> +#include <amdblocks/acpimmio.h> +#include <amdblocks/reset.h> +#include <assert.h> + +/* TODO: add <fsp/util.h> back during FSP integration */ + +void set_warm_reset_flag(void) +{ + uint8_t ncp = inw(NCP_ERR); + + outb(NCP_ERR, ncp | NCP_WARM_BOOT); +} + +int is_warm_reset(void) +{ + return !!(inb(NCP_ERR) & NCP_WARM_BOOT); +} + +void do_cold_reset(void) +{ + /* De-assert and then assert all PwrGood signals on CF9 reset. */ + pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | + TOGGLE_ALL_PWR_GOOD); + outb(RST_CPU | SYS_RST, RST_CNT); +} + +void do_warm_reset(void) +{ + set_warm_reset_flag(); + + /* Assert reset signals only. */ + outb(RST_CPU | SYS_RST, RST_CNT); +} + +void do_board_reset(void) +{ + /* TODO: Would a warm_reset() suffice? */ + do_cold_reset(); +} + +void chipset_handle_reset(uint32_t status) +{ + printk(BIOS_ERR, "Error: unexpected call to %s(0x%08x). Doing cold reset.\n", + __func__, status); + BUG(); + do_cold_reset(); +}
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48488 )
Change subject: soc/amd/cezanne: add 0xcf9 reset ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48488/1/src/soc/amd/cezanne/reset.c File src/soc/amd/cezanne/reset.c:
https://review.coreboot.org/c/coreboot/+/48488/1/src/soc/amd/cezanne/reset.c... PS1, Line 53: BUG(); Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON()
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48488 )
Change subject: soc/amd/cezanne: add 0xcf9 reset ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48488/2/src/soc/amd/cezanne/reset.c File src/soc/amd/cezanne/reset.c:
https://review.coreboot.org/c/coreboot/+/48488/2/src/soc/amd/cezanne/reset.c... PS2, Line 53: BUG(); Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON()
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48488 )
Change subject: soc/amd/cezanne: add 0xcf9 reset ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48488/3/src/soc/amd/cezanne/reset.c File src/soc/amd/cezanne/reset.c:
https://review.coreboot.org/c/coreboot/+/48488/3/src/soc/amd/cezanne/reset.c... PS3, Line 53: BUG(); Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON()
Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48488 )
Change subject: soc/amd/cezanne: add 0xcf9 reset ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48488/3/src/soc/amd/cezanne/reset.c File src/soc/amd/cezanne/reset.c:
https://review.coreboot.org/c/coreboot/+/48488/3/src/soc/amd/cezanne/reset.c... PS3, Line 49: void chipset_handle_reset(uint32_t status) Hmm, how did this build correctly? This is prototyped in src/drivers/intel/fsp2_0/include/fsp/util.h. Did one of our other header files include it for us?
Could consider adding this function later. Also, beyond the scope of this patch, this function could be commonized, similar to soc/intel/common/fsp_reset.
Outside
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48488 )
Change subject: soc/amd/cezanne: add 0xcf9 reset ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48488/3/src/soc/amd/cezanne/reset.c File src/soc/amd/cezanne/reset.c:
https://review.coreboot.org/c/coreboot/+/48488/3/src/soc/amd/cezanne/reset.c... PS3, Line 49: void chipset_handle_reset(uint32_t status)
Hmm, how did this build correctly? This is prototyped in src/drivers/intel/fsp2_0/include/fsp/util. […]
https://review.coreboot.org/c/coreboot/+/48488/3/src/soc/amd/cezanne/include... has the function prototype. factoring that out to the common code that only gets added when the fsp is already integrated sounds like a good idea though
Hello build bot (Jenkins), Jason Glenesk, Patrick Georgi, Martin Roth, Marshall Dawson,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48488
to look at the new patch set (#4).
Change subject: soc/amd/cezanne: add 0xcf9 reset ......................................................................
soc/amd/cezanne: add 0xcf9 reset
This also temporary adds a prototype for chipset_handle_reset that will be removed when the FSP integration gets added.
Change-Id: Ibb78661c102e0d0327f3e74173bf98bc40e13960 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/mainboard/amd/majolica/Kconfig M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/cezanne/include/soc/iomap.h A src/soc/amd/cezanne/include/soc/reset.h M src/soc/amd/cezanne/include/soc/southbridge.h A src/soc/amd/cezanne/reset.c 7 files changed, 67 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/48488/4
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48488 )
Change subject: soc/amd/cezanne: add 0xcf9 reset ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48488/3/src/soc/amd/cezanne/reset.c File src/soc/amd/cezanne/reset.c:
https://review.coreboot.org/c/coreboot/+/48488/3/src/soc/amd/cezanne/reset.c... PS3, Line 49: void chipset_handle_reset(uint32_t status)
https://review.coreboot.org/c/coreboot/+/48488/3/src/soc/amd/cezanne/include.... […]
Done in CB:48537
Mathew King has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48488 )
Change subject: soc/amd/cezanne: add 0xcf9 reset ......................................................................
Patch Set 4: Code-Review+2
Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48488 )
Change subject: soc/amd/cezanne: add 0xcf9 reset ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48488/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48488/4//COMMIT_MSG@9 PS4, Line 9: adds a prototype for chipset_handle_reset should go away now
Hello build bot (Jenkins), Jason Glenesk, Patrick Georgi, Martin Roth, Marshall Dawson, Mathew King,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48488
to look at the new patch set (#5).
Change subject: soc/amd/cezanne: add 0xcf9 reset ......................................................................
soc/amd/cezanne: add 0xcf9 reset
Change-Id: Ibb78661c102e0d0327f3e74173bf98bc40e13960 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/mainboard/amd/majolica/Kconfig M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/cezanne/include/soc/iomap.h A src/soc/amd/cezanne/include/soc/reset.h M src/soc/amd/cezanne/include/soc/southbridge.h A src/soc/amd/cezanne/reset.c 7 files changed, 67 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/48488/5
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48488 )
Change subject: soc/amd/cezanne: add 0xcf9 reset ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48488/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48488/4//COMMIT_MSG@9 PS4, Line 9: adds a prototype for chipset_handle_reset
should go away now
ah, forgot to remove that. fixed now
Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48488 )
Change subject: soc/amd/cezanne: add 0xcf9 reset ......................................................................
Patch Set 5: Code-Review+2
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48488 )
Change subject: soc/amd/cezanne: add 0xcf9 reset ......................................................................
soc/amd/cezanne: add 0xcf9 reset
Change-Id: Ibb78661c102e0d0327f3e74173bf98bc40e13960 Signed-off-by: Felix Held felix-coreboot@felixheld.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/48488 Reviewed-by: Marshall Dawson marshalldawson3rd@gmail.com Reviewed-by: Mathew King mathewk@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/amd/majolica/Kconfig M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/cezanne/include/soc/iomap.h A src/soc/amd/cezanne/include/soc/reset.h M src/soc/amd/cezanne/include/soc/southbridge.h A src/soc/amd/cezanne/reset.c 7 files changed, 67 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Mathew King: Looks good to me, approved
diff --git a/src/mainboard/amd/majolica/Kconfig b/src/mainboard/amd/majolica/Kconfig index f811c39..cb3237c 100644 --- a/src/mainboard/amd/majolica/Kconfig +++ b/src/mainboard/amd/majolica/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select SOC_AMD_CEZANNE - select MISSING_BOARD_RESET
config FMDFILE string diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index be45de4..be4d432 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -13,6 +13,7 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 + select HAVE_CF9_RESET select IOAPIC select RESET_VECTOR_IN_RAM select SOC_AMD_COMMON diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index e7d0aea..353bdbe 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -7,10 +7,15 @@
bootblock-y += bootblock.c bootblock-y += early_fch.c +bootblock-y += reset.c
+verstage_x86-y += reset.c + +romstage-y += reset.c romstage-y += romstage.c
ramstage-y += chip.c +ramstage-y += reset.c
CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include
diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h index 96313ea..4d47f7e 100644 --- a/src/soc/amd/cezanne/include/soc/iomap.h +++ b/src/soc/amd/cezanne/include/soc/iomap.h @@ -4,6 +4,7 @@ #define AMD_CEZANNE_IOMAP_H
/* I/O Ranges */ -#define SMB_BASE_ADDR 0xb00 +#define NCP_ERR 0x00f0 +#define SMB_BASE_ADDR 0x0b00
#endif /* AMD_CEZANNE_IOMAP_H */ diff --git a/src/soc/amd/cezanne/include/soc/reset.h b/src/soc/amd/cezanne/include/soc/reset.h new file mode 100644 index 0000000..4cb94ce --- /dev/null +++ b/src/soc/amd/cezanne/include/soc/reset.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_CEZANNE_RESET_H +#define AMD_CEZANNE_RESET_H + +void set_warm_reset_flag(void); +int is_warm_reset(void); + +#endif /* AMD_CEZANNE_RESET_H */ diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index 2456ebc..03ee2bb 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -5,6 +5,13 @@
#include <soc/iomap.h>
+/* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */ +#define PWR_RESET_CFG 0x10 +#define TOGGLE_ALL_PWR_GOOD (1 << 1) + +/* IO 0xf0 NCP Error */ +#define NCP_WARM_BOOT (1 << 7) /* Write-once */ + void fch_pre_init(void); void fch_early_init(void);
diff --git a/src/soc/amd/cezanne/reset.c b/src/soc/amd/cezanne/reset.c new file mode 100644 index 0000000..89b5b80 --- /dev/null +++ b/src/soc/amd/cezanne/reset.c @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/io.h> +#include <cf9_reset.h> +#include <reset.h> +#include <soc/reset.h> +#include <soc/southbridge.h> +#include <amdblocks/acpimmio.h> +#include <amdblocks/reset.h> + +void set_warm_reset_flag(void) +{ + uint8_t ncp = inw(NCP_ERR); + + outb(NCP_ERR, ncp | NCP_WARM_BOOT); +} + +int is_warm_reset(void) +{ + return !!(inb(NCP_ERR) & NCP_WARM_BOOT); +} + +void do_cold_reset(void) +{ + /* De-assert and then assert all PwrGood signals on CF9 reset. */ + pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | + TOGGLE_ALL_PWR_GOOD); + outb(RST_CPU | SYS_RST, RST_CNT); +} + +void do_warm_reset(void) +{ + set_warm_reset_flag(); + + /* Assert reset signals only. */ + outb(RST_CPU | SYS_RST, RST_CNT); +} + +void do_board_reset(void) +{ + /* TODO: Would a warm_reset() suffice? */ + do_cold_reset(); +}
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build bot (Jenkins) (Code Review) -
Felix Held (Code Review)
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Marshall Dawson (Code Review)
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Mathew King (Code Review)