Felix Held uploaded patch set #4 to this change.
soc/amd/cezanne: add 0xcf9 reset
This also temporary adds a prototype for chipset_handle_reset that will
be removed when the FSP integration gets added.
Change-Id: Ibb78661c102e0d0327f3e74173bf98bc40e13960
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
---
M src/mainboard/amd/majolica/Kconfig
M src/soc/amd/cezanne/Kconfig
M src/soc/amd/cezanne/Makefile.inc
M src/soc/amd/cezanne/include/soc/iomap.h
A src/soc/amd/cezanne/include/soc/reset.h
M src/soc/amd/cezanne/include/soc/southbridge.h
A src/soc/amd/cezanne/reset.c
7 files changed, 67 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/48488/4
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