HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31027
Change subject: nb/intel/i945: Use macro instead of magic number ......................................................................
nb/intel/i945: Use macro instead of magic number
Change-Id: I028013bd7511b5b9fc80e5f744fcad584cb25fd3 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/raminit.c 2 files changed, 14 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/31027/1
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 09a18e3..bc2f6f9 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -160,10 +160,10 @@ pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, 0x80); /* ACPI_CNTL: Enable ACPI BAR */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x80); /* ACPI_CNTL: Enable ACPI BAR */
pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c, 0x10); /* GC: Enable GPIOs */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), GPIO_CNTL, 0x10); /* GC: Enable GPIOs */ setup_pch_gpios(&mainboard_gpio_map); printk(BIOS_DEBUG, " done.\n");
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 64c87da..ff866aa 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -246,13 +246,13 @@ u8 reg8; u8 do_reset = 0;
- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2);
if (reg8 & ((1<<7)|(1<<2))) { if (reg8 & (1<<2)) { printk(BIOS_DEBUG, "SLP S4# Assertion Width Violation.\n"); /* Write back clears bit 2 */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); do_reset = 1;
} @@ -260,14 +260,14 @@ if (reg8 & (1<<7)) { printk(BIOS_DEBUG, "DRAM initialization was interrupted.\n"); reg8 &= ~(1<<7); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); do_reset = 1; }
/* Set SLP_S3# Assertion Stretch Enable */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); /* GEN_PMCON_3 */ + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); reg8 |= (1 << 3); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
if (do_reset) { printk(BIOS_DEBUG, "Reset required.\n"); @@ -278,9 +278,9 @@ }
/* Set DRAM initialization bit in ICH7 */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); reg8 |= (1<<7); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8);
/* clear self refresh status if check is disabled or not a resume */ if (!CONFIG_CHECK_SLFRCS_ON_RESUME @@ -1810,9 +1810,9 @@ */ goto cache_code; vco_update: - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); reg8 &= ~(1 << 7); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8);
clkcfg &= ~(1 << 10); MCHBAR32(CLKCFG) = clkcfg; @@ -2415,7 +2415,7 @@ MCHBAR32(REPC) |= (1 << 0);
/* enable upper CMOS */ - RCBA32(0x3400) = (1 << 2); + RCBA32(RC) = (1 << 2);
/* Program Receive Enable Timings */ if (sysinfo->boot_path == BOOT_PATH_RESUME) { @@ -2829,9 +2829,9 @@ sdram_enable_rcomp();
/* Tell ICH7 that we're done */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); reg8 &= ~(1 << 7); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8);
printk(BIOS_DEBUG, "RAM initialization finished.\n");
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31027 )
Change subject: nb/intel/i945: Use macro instead of magic number ......................................................................
Patch Set 1:
(4 comments)
https://review.coreboot.org/#/c/31027/1/src/northbridge/intel/i945/early_ini... File src/northbridge/intel/i945/early_init.c:
https://review.coreboot.org/#/c/31027/1/src/northbridge/intel/i945/early_ini... PS1, Line 163: pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x80); /* ACPI_CNTL: Enable ACPI BAR */ line over 80 characters
https://review.coreboot.org/#/c/31027/1/src/northbridge/intel/i945/early_ini... PS1, Line 166: pci_write_config8(PCI_DEV(0, 0x1f, 0), GPIO_CNTL, 0x10); /* GC: Enable GPIOs */ line over 80 characters
https://review.coreboot.org/#/c/31027/1/src/northbridge/intel/i945/raminit.c File src/northbridge/intel/i945/raminit.c:
https://review.coreboot.org/#/c/31027/1/src/northbridge/intel/i945/raminit.c... PS1, Line 255: pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); line over 80 characters
https://review.coreboot.org/#/c/31027/1/src/northbridge/intel/i945/raminit.c... PS1, Line 263: pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); line over 80 characters
Hello Patrick Rudolph, Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31027
to look at the new patch set (#2).
Change subject: nb/intel/i945: Use macro instead of magic number ......................................................................
nb/intel/i945: Use macro instead of magic number
Change-Id: I028013bd7511b5b9fc80e5f744fcad584cb25fd3 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/raminit.c M src/southbridge/intel/i82801gx/i82801gx.h 3 files changed, 15 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/31027/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31027 )
Change subject: nb/intel/i945: Use macro instead of magic number ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/#/c/31027/2/src/northbridge/intel/i945/raminit.c File src/northbridge/intel/i945/raminit.c:
https://review.coreboot.org/#/c/31027/2/src/northbridge/intel/i945/raminit.c... PS2, Line 255: pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); line over 80 characters
https://review.coreboot.org/#/c/31027/2/src/northbridge/intel/i945/raminit.c... PS2, Line 263: pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); line over 80 characters
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31027 )
Change subject: nb/intel/i945: Use macro instead of magic number ......................................................................
Patch Set 2: Code-Review+1
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31027 )
Change subject: nb/intel/i945: Use macro instead of magic number ......................................................................
Patch Set 2: Code-Review+1
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31027 )
Change subject: nb/intel/i945: Use macro instead of magic number ......................................................................
Patch Set 2: Code-Review+2
Hello Patrick Rudolph, Angel Pons, Paul Menzel, build bot (Jenkins), Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31027
to look at the new patch set (#3).
Change subject: nb/intel/i945: Use macro instead of magic number ......................................................................
nb/intel/i945: Use macro instead of magic number
Change-Id: I028013bd7511b5b9fc80e5f744fcad584cb25fd3 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/raminit.c M src/southbridge/intel/i82801gx/i82801gx.h 3 files changed, 14 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/31027/3
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31027 )
Change subject: nb/intel/i945: Use macro instead of magic number ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/#/c/31027/3/src/northbridge/intel/i945/raminit.c File src/northbridge/intel/i945/raminit.c:
https://review.coreboot.org/#/c/31027/3/src/northbridge/intel/i945/raminit.c... PS3, Line 256: pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); line over 80 characters
https://review.coreboot.org/#/c/31027/3/src/northbridge/intel/i945/raminit.c... PS3, Line 264: pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); line over 80 characters
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31027 )
Change subject: nb/intel/i945: Use macro instead of magic number ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/#/c/31027/4/src/northbridge/intel/i945/raminit.c File src/northbridge/intel/i945/raminit.c:
https://review.coreboot.org/#/c/31027/4/src/northbridge/intel/i945/raminit.c... PS4, Line 256: pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); line over 80 characters
https://review.coreboot.org/#/c/31027/4/src/northbridge/intel/i945/raminit.c... PS4, Line 264: pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); line over 80 characters
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31027 )
Change subject: nb/intel/i945: Use macro instead of magic number ......................................................................
Patch Set 4: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31027 )
Change subject: nb/intel/i945: Use macro instead of magic number ......................................................................
nb/intel/i945: Use macro instead of magic number
Change-Id: I028013bd7511b5b9fc80e5f744fcad584cb25fd3 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/31027 Reviewed-by: Patrick Rudolph siro@das-labor.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/raminit.c M src/southbridge/intel/i82801gx/i82801gx.h 3 files changed, 14 insertions(+), 13 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 274296d..84d9c10 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -158,10 +158,10 @@ printk(BIOS_DEBUG, "Setting up static southbridge registers...");
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, 0x80); /* ACPI_CNTL: Enable ACPI BAR */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, ACPI_EN);
pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c, 0x10); /* GC: Enable GPIOs */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), GPIO_CNTL, GPIO_EN); setup_pch_gpios(&mainboard_gpio_map); printk(BIOS_DEBUG, " done.\n");
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 0cf03ae..74407c1 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -247,13 +247,13 @@ u8 reg8; u8 do_reset = 0;
- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2);
if (reg8 & ((1<<7)|(1<<2))) { if (reg8 & (1<<2)) { printk(BIOS_DEBUG, "SLP S4# Assertion Width Violation.\n"); /* Write back clears bit 2 */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); do_reset = 1;
} @@ -261,14 +261,14 @@ if (reg8 & (1<<7)) { printk(BIOS_DEBUG, "DRAM initialization was interrupted.\n"); reg8 &= ~(1<<7); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); do_reset = 1; }
/* Set SLP_S3# Assertion Stretch Enable */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); /* GEN_PMCON_3 */ + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); reg8 |= (1 << 3); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
if (do_reset) { printk(BIOS_DEBUG, "Reset required.\n"); @@ -277,9 +277,9 @@ }
/* Set DRAM initialization bit in ICH7 */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); reg8 |= (1<<7); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8);
/* clear self refresh status if check is disabled or not a resume */ if (!CONFIG(CHECK_SLFRCS_ON_RESUME) @@ -1807,9 +1807,9 @@ */ goto cache_code; vco_update: - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); reg8 &= ~(1 << 7); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8);
clkcfg &= ~(1 << 10); MCHBAR32(CLKCFG) = clkcfg; @@ -2813,9 +2813,9 @@ sdram_enable_rcomp();
/* Tell ICH7 that we're done */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); reg8 &= ~(1 << 7); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8);
printk(BIOS_DEBUG, "RAM initialization finished.\n");
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index b693b75..a91ffc5 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -94,6 +94,7 @@ #define BIOS_CNTL 0xDC #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ +#define GPIO_EN (1 << 4)
#define PIRQA_ROUT 0x60 #define PIRQB_ROUT 0x61
-
Angel Pons (Code Review) -
build bot (Jenkins) (Code Review)
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HAOUAS Elyes (Code Review)
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Patrick Georgi (Code Review)
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Patrick Rudolph (Code Review)
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Paul Menzel (Code Review)