Change in coreboot[master]: drivers/intel/fsp1_1: Configure UART after memory init

[Frans Hendriks (Code Review)]

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28464 )

Change subject: drivers/intel/fsp1_1: Configure UART after memory init
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Patch Set 4:
> Patch Set 4:
>
> Heads up - Somebody from Intel commented on https://github.com/IntelFsp/FSP/issues/15 and says it has something to do with coreboot setting the UARTs to ACPI mode. The suggested fix is to conditionally set PcdEnableHsuart0 and PcdEnableHsuart1 (see the issue on Github for details).

Intel provided fix in routine, which is not available in coreboot (Intel fix is based on soc\intel\fsp_braswell where coreboot uses soc\intel\braswell).
The problem is not the configuration of the HSUART, but the internal UART is enabled. Having this internal UART enabled, causes external UART (0x3F8) can not be used/accessed.

FSP enables the internal using 'SerialPortEnable' which is a build option and can not be configured external.

Imo this issue has not a coreboot cause, but still an Intel FSP bug.