Attention is currently required from: Reka Norman, Paul Menzel, Rizwan Qureshi, Krishna P Bhat D, Usha P, Patrick Rudolph, Kangheui Won. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59752 )
Change subject: soc/intel/alderlake: Configure 9 I/O for ADL-N ......................................................................
Patch Set 2:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59752/comment/57f8de1c_e4e80fb5 PS2, Line 7: Configure 9 I/O for ADL-N don't able to follow what is `9` here.
Looking at code, you are just configuring PCIe RP like RP Number, ClkSrC and ClkReq. Why not specify the same ?
File src/soc/intel/alderlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/59752/comment/ea83a692_92f87b0b PS2, Line 177: default Please take a look into this
https://chrome-internal.googlesource.com/chromeos/third_party/intel-fsp/adl/...
The doc that you have shared here page 32 looks data incomplete
if you download 645550 doc chapter 21 tell me there are 12 RPs as below.
PCIe* Interface (D28:F0-F7 and D29:F0-F3) Registers Summary
https://review.coreboot.org/c/coreboot/+/59752/comment/527154bf_a3ad41b2 PS2, Line 193: default 5 if SOC_INTEL_ALDERLAKE_PCH_N also check this
https://chrome-internal.googlesource.com/chromeos/third_party/intel-fsp/adl/...
https://review.coreboot.org/c/coreboot/+/59752/comment/d7b55b7d_837fd941 PS2, Line 199: default 5 if SOC_INTEL_ALDERLAKE_PCH_N same as above
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Subrata Banik (Code Review)