Attention is currently required from: Reka Norman, Paul Menzel, Rizwan Qureshi, Krishna P Bhat D, Usha P, Patrick Rudolph, Kangheui Won.
4 comments:
Commit Message:
Patch Set #2, Line 7: Configure 9 I/O for ADL-N
don't able to follow what is `9` here.
Looking at code, you are just configuring PCIe RP like RP Number, ClkSrC and ClkReq. Why not specify the same ?
File src/soc/intel/alderlake/Kconfig:
Patch Set #2, Line 177: default
Please take a look into this
https://chrome-internal.googlesource.com/chromeos/third_party/intel-fsp/adl/+/refs/heads/chromeos/ClientOneSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PchInfoLibAdl.c#678
The doc that you have shared here page 32 looks data incomplete
if you download 645550 doc chapter 21 tell me there are 12 RPs as below.
PCIe* Interface (D28:F0-F7 and D29:F0-F3)
Registers Summary
Patch Set #2, Line 193: default 5 if SOC_INTEL_ALDERLAKE_PCH_N
also check this
https://chrome-internal.googlesource.com/chromeos/third_party/intel-fsp/adl/+/refs/heads/chromeos/ClientOneSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PchInfoLibAdl.c#574
Patch Set #2, Line 199: default 5 if SOC_INTEL_ALDERLAKE_PCH_N
same as above
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