Change in coreboot[master]: soc/intel/broadwell/xhci.c: Align with Lynx Point

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45721 )

Change subject: soc/intel/broadwell/xhci.c: Align with Lynx Point
......................................................................

soc/intel/broadwell/xhci.c: Align with Lynx Point

Change-Id: Idf40e2687b064c5ec7834e3c7d7ea9c8cb83c882
Signed-off-by: Angel Pons 
---
M src/soc/intel/broadwell/xhci.c
1 file changed, 2 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/45721/1

diff --git a/src/soc/intel/broadwell/xhci.c b/src/soc/intel/broadwell/xhci.c
index 319c9b1..6d824a5 100644
--- a/src/soc/intel/broadwell/xhci.c
+++ b/src/soc/intel/broadwell/xhci.c
@@ -138,18 +138,13 @@
    	return;

/* Set D0 state */
-	reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS);
-	reg16 &= ~XHCI_PWR_CTL_SET_MASK;
-	reg16 |= XHCI_PWR_CTL_SET_D0;
-	pci_write_config16(dev, XHCI_PWR_CTL_STS, reg16);
+	pci_update_config16(dev, XHCI_PWR_CTL_STS, ~PWR_CTL_SET_MASK, PWR_CTL_SET_D0);

if (!is_broadwell) {
    	/* This WA is only for lpt */

/* Clear PCI 0xB0[14:13] */
-		reg32 = pci_read_config32(dev, 0xb0);
-		reg32 &= ~((1 << 14) | (1 << 13));
-		pci_write_config32(dev, 0xb0, reg32);
+		pci_and_config32(dev, 0xb0, ~((1 << 14) | (1 << 13)));

/* Clear MMIO 0x816c[14,2] */
    	reg32 = read32(mem_base + 0x816c);

[Angel Pons (Code Review)]

Hello build bot (Jenkins), Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/45721

to look at the new patch set (#2).

Change subject: soc/intel/broadwell/xhci.c: Align with Lynx Point
......................................................................

soc/intel/broadwell/xhci.c: Align with Lynx Point

Change-Id: Idf40e2687b064c5ec7834e3c7d7ea9c8cb83c882
Signed-off-by: Angel Pons 
---
M src/soc/intel/broadwell/xhci.c
1 file changed, 2 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/45721/2

[Matt DeVillier (Code Review)]

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45721 )

Change subject: soc/intel/broadwell/xhci.c: Align with Lynx Point
......................................................................

Patch Set 4: Code-Review+1

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45721 )

Change subject: soc/intel/broadwell/xhci.c: Align with Lynx Point
......................................................................

Patch Set 4: Code-Review+2

[Nico Huber (Code Review)]

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45721 )

Change subject: soc/intel/broadwell/xhci.c: Align with Lynx Point
......................................................................

soc/intel/broadwell/xhci.c: Align with Lynx Point

Change-Id: Idf40e2687b064c5ec7834e3c7d7ea9c8cb83c882
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45721
Reviewed-by: Matt DeVillier 
Reviewed-by: Tim Wawrzynczak 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/broadwell/xhci.c
1 file changed, 2 insertions(+), 8 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Matt DeVillier: Looks good to me, but someone else must approve
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/soc/intel/broadwell/xhci.c b/src/soc/intel/broadwell/xhci.c
index 319c9b1..526781d 100644
--- a/src/soc/intel/broadwell/xhci.c
+++ b/src/soc/intel/broadwell/xhci.c
@@ -129,7 +129,6 @@
 /* Handler for XHCI controller on entry to S3/S4/S5 */
 void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ)
 {
-	u16 reg16;
    u32 reg32;
    u8 *mem_base = usb_xhci_mem_base(dev);
    u8 is_broadwell = !!(cpu_family_model() == BROADWELL_FAMILY_ULT);
@@ -138,18 +137,13 @@
    	return;

/* Set D0 state */
-	reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS);
-	reg16 &= ~XHCI_PWR_CTL_SET_MASK;
-	reg16 |= XHCI_PWR_CTL_SET_D0;
-	pci_write_config16(dev, XHCI_PWR_CTL_STS, reg16);
+	pci_update_config16(dev, XHCI_PWR_CTL_STS, ~XHCI_PWR_CTL_SET_MASK, XHCI_PWR_CTL_SET_D0);

if (!is_broadwell) {
    	/* This WA is only for lpt */

/* Clear PCI 0xB0[14:13] */
-		reg32 = pci_read_config32(dev, 0xb0);
-		reg32 &= ~((1 << 14) | (1 << 13));
-		pci_write_config32(dev, 0xb0, reg32);
+		pci_and_config32(dev, 0xb0, ~((1 << 14) | (1 << 13)));

/* Clear MMIO 0x816c[14,2] */
    	reg32 = read32(mem_base + 0x816c);